Array and moat isolation structures and method of manufacture

A method comprising:

• forming a deep trench for a DRAM array, the deep trench for the DRAM array having a first critical dimension;
• forming a deep trench for a moat region having a second critical dimension, larger than the first critical dimension;
• lining the deep trench for the DRAM array and the deep trench for the moat region with a dielectric material;
• filling the deep trench for the DRAM array with metal, formed over the dielectric material;
• lining the deep trench for the moat region with the metal, at a same time as the filling step, wherein the metal lining the deep trench has a dimension smaller than that of the metal filling the deep trench for the DRAM array;
• filling the deep trench for the moat region with a material, formed over the metal;
• and
• recessing the metal in the moat region and DRAM array, using a same etching process, wherein the metal in the DRAM array is recessed more than the metal in the moat region due to RIE lag.

A structure, comprising:

• a deep trench for a DRAM array having a first critical dimension;
• a deep trench for a moat region having a second critical dimension, larger than the first critical dimension;
• a dielectric node lining the deep trench for the DRAM array and the deep trench for the moat region;
• a metal filling the first critical dimension of the deep trench for the DRAM array, formed over the dielectric node;
• a metal lining over the dielectric node in the deep trench for the moat region, wherein the metal lining has a dimension smaller than that of the metal filling the first critical dimension of the deep trench for the DRAM array;
• and
• a Si material formed over the metal in the deep trench for the moat region, wherein
• the metal in the DRAM array is lower than the metal in the moat region due to RIE lag.