Shallow trench isolation structure having a nitride plug
AssigneeInternational Business Machines Corporation
InventorsByeong Y. Kim, Shreesh Narasimha
Life of this patent
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Abstract
A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
Claims25
A semiconductor device comprising:
- a substrate;
- one or more trenches in the substrate;
- a shallow trench isolation structure having one or more oxide layers and a nitride plug, wherein the shallow trench isolation structure is formed on and adjacent to at least one of the one or more trenches;
- one or more gates formed on the substrate and spaced at a distance from each other;
- and
- a dielectric layer formed on and adjacent to the substrate, the shallow trench isolation structure, and the one or more gates.
A method of forming a semiconductor device, the method comprising:
- forming a pad oxide layer on a substrate;
- forming a pad nitride layer on the pad oxide layer;
- forming one or more trenches through the pad nitride layer, the pad oxide layer, and into the substrate;
- forming a liner oxide layer on the pad nitride layer, and on and adjacent to the one or more trenches;
- forming a first layer of high density plasma (HDP) oxide on and adjacent to the liner oxide layer;
- forming a nitride layer on and adjacent to the HDP oxide in at least one of the one or more trenches;
- removing a portion of the nitride layer, which forms a nitride plug that remains on and adjacent to the HDP oxide in the at least one of the one or more trenches;
- forming a second layer of the HDP oxide on the nitride plug, wherein the nitride plug is encapsulated in the HDP oxide;
- planarizing a portion of the HDP oxide and a portion of the liner oxide layer, wherein the HDP oxide, the liner oxide layer, and the nitride plug remain in the at least one of the one or more trenches;
- removing the pad nitride layer, the pad oxide layer, a portion of the liner oxide layer, and a portion of the HDP oxide in which a shallow trench isolation structure is formed in the at least one of the one or more trenches;
- forming one or more gates on the substrate, wherein the one or more gates are spaced at a distance from each other;
- and
- forming a dielectric layer on and adjacent to the substrate, the one or more gates, and the shallow trench isolation structure.
A method of forming a semiconductor device, the method comprising:
- forming a substrate;
- forming one or more trenches in the substrate;
- forming a shallow trench isolation structure having one or more oxide layers and a nitride plug, wherein the shallow trench isolation structure is on and adjacent to at least one of the one or more trenches;
- forming one or more gates on the substrate and spaced at a distance from each other;
- and
- forming a dielectric layer on and adjacent to the substrate, the shallow trench isolation structure, and the one or more gates.
Dependencies are inferred from the claim text.