High-k dielectric and silicon nitride box region
AssigneeInternational Business Machines Corporation
InventorsEFFENDI LEOBANDUNG, Dae-Gyu Park, Shom S. Ponoth, Zhibin Ren, Ghavam G. Shahidi, Leathen Shi
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Abstract
Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.
Claims20
A semiconductor structure, comprising:
- a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including:
- at least one silicon nitride layer;
- and
- a high-k dielectric layer;
- and
- a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.
A method of forming a semiconductor structure, the method comprising:
- providing a donor wafer including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer;
- depositing a silicon nitride layer atop the SOI layer;
- depositing a high-k dielectric layer atop the silicon nitride layer;
- sealing the high-k dielectric layer;
- and
- bonding a bulk silicon wafer to the high-k dielectric layer.
A semiconductor structure, comprising:
- a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including;
- a first silicon nitride layer and a second silicon nitride layer;
- and
- a high-k dielectric layer therebetween;
- and
- a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.
Dependencies are inferred from the claim text.