Back to results
US 2013/0093022 A1Published application
Semiconductor device
OwnerHyun-Seung CHOIinventor
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a transistor area includes a transistor area comprising a transistor formed in the transistor area at a transistor level, wherein a gate of the transistor is formed at a gate level; a first metal line formed across the transistor area at a first level higher than the transistor level to supply a power voltage to the transistor; and a gate metal line formed at the gate level to supply the power voltage to the transistor area, and the gate metal line is electrically coupled to the first metal line.
Claims18
A semiconductor device comprising:
- a transistor area comprising a transistor formed in the transistor area at a transistor level, wherein a gate of the transistor is formed at a gate level;
- a first metal line formed across the transistor area at a first level higher than the transistor level to supply a power voltage to the transistor;
- and
- a gate metal line formed at the gate level to supply the power voltage to the transistor area, and the gate metal line is electrically coupled to the first metal line.
1 more element
A semiconductor device comprising:
- a PMOS area comprising a PMOS transistor formed in the PMOS area at a transistor level, wherein a gate of the PMOS transistor is formed at a gate level;
- a first metal line formed across the PMOS area at a first level higher than the transistor level to supply a power supply voltage to the PMOS transistor;
- a first gate metal line formed at the gate level to supply the power supply voltage to the PMOS area, and the first metal gate metal line is electrically coupled to the first metal line;
- an NMOS area spaced apart from the PMOS area and comprising an NMOS transistor formed in the NMOS area at a transistor level, wherein a gate of the PMOS transistor is formed at the gate level;
- a second metal line formed across the NMOS area at the first level to supply a ground voltage to the NMOS transistor;
- and
- a second gate metal line formed at the gate level to supply the ground voltage to the NMOS area, and the second gate metal line is electrically coupled to the second metal line.
4 more elements
A semiconductor device comprising:
- a transistor comprising an active area formed at an active area level and a gate formed at a gate level higher than the active area level and adjacent to the active area;
- a gate metal line formed at the gate level to supply a power voltage to the transistor;
- a first metal line formed at a first level higher than the gate level to supply the power voltage to the transistor, and the first metal line is electrically coupled to the gate metal line;
- and
- a second metal line formed at a second level higher than the gate level and lower than the first level coupled to the active area of the transistor through a first contact, coupled to the gate metal line through a second contact, and coupled to the first metal line through a third contact.
2 more elements
Dependencies are inferred from the claim text.