Semiconductor memory apparatus and method for fabricating the same
AssigneeSK hynix Inc.
InventorsHyoung Soon YUNE, Joo Hong JEONG
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Abstract
A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.
Claims5
A semiconductor memory apparatus, comprising:
- an isolation layer defining an active region in a cell region and a peripheral region;
- a buried word line and a gate line disposed in the cell region and the peripheral region respectively;
- and
- a connection pad disposed in the isolation layer and coupled to the gate line.
Dependencies are inferred from the claim text.