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US 2013/0086453 A1Published application
Systems and methods involving managing a problematic memory cell
AssigneeMicron Technology, Inc.
InventorsKenneth James Eldredge, Larry Joseph Koudele
Life of this patent
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Abstract
Subject matter described pertains to managing problematic memory cells in a memory array.
Claims23
A system comprising:
- a memory array;
- and
- a controller capable of identifying a memory cell of the array that approximates either a short circuit or an open circuit as problematic.
A method, comprising:
- applying a programming signal to a memory cell;
- determining whether the programming signal programs the memory cell approximately within an operational range of a physical property of the memory cell;
- and
- identifying a symbol within a codeword corresponding to an information state read from the memory cell if the memory cell was not programmed approximately within the operational range of the physical property.
1 more element
A method of managing a problematic memory cell using an error control code, comprising:
- determining whether a memory cell is problematic;
- and
- setting a flag in a codeword if the memory cell is determined to be problematic, the flag identifying a symbol of the codeword within which an information state read from the problematic memory cell is located.
A system comprising:
- an array of memory cells;
- a controller coupled to the array of memory cells, wherein the controller is capable of:
- determining whether a memory cell of the array is programmed approximately within an operational range of a physical property of the memory cell;
- and
- providing a flag that identifies a symbol of a codeword as corresponding to an information state read from a problematic memory cell if it is determined that the memory cell was not programmed within the operational range.
2 more elements
Dependencies are inferred from the claim text.