Scalable Decode-Time Instruction Sequence Optimization of Dependent Instructions

A computer implemented method for executing dependent instructions of an instruction set architecture (ISA) out-of-order out-of-order, the computer implemented method comprising:

• fetching for execution, by the processor, a first instruction of the ISA and a second instruction of the ISA;
• determining in-order execution candidacy, by the processor, of the first instruction and the second instruction, wherein the first instruction and second instruction are configured to be executed out-of-order but are candidates to be effectively executed in-order, the determination comprising determining that the first instruction specifies a target operand location for a target operand and the second instruction specifies a source operand location for a source operand, wherein the first instruction is configured to store a target operand at the target operand location, wherein the source operand location is the same as the target operand location, wherein the second instruction is configured to obtain the source operand at the source operand location;
• and
• based on the determining in-order execution candidacy, effectively executing, by the processor, the first instruction and the second instruction by executing, by the processor, the first instruction of the ISA and a new second instruction not of the ISA, wherein the new second instruction is not dependent on the target operand of the first instruction.