Memory system and memory interface device

A memory interface circuit comprising:

• an access control circuit that is connected to a plurality of memory circuits and receives a row address and a first command, then receives a column address and a second command from a memory access source and identifies a designated one memory circuit among the plurality of memory circuits by the column address received, performs an access control to the designated one memory,
• wherein the access control circuit performs a speculative access to the plurality of memory circuits when receiving the row command and the first command and sends the second command the designated one memory circuit by the column address and sends a third command that cancel the speculative access to other memory circuits that is not designated by the column address when receiving the column address and the second command.

A memory interface device comprising;

• an access control circuit that is connected to a plurality of memory circuits and receives a row address and a first command, then receives a column address and a second command from a memory access source and identifies a designated one memory circuit among the plurality of memory circuits by the column address received,
• wherein the access control circuit performs a speculative access to the plurality of memory circuits when receiving the row command and the first command and sends the second command to the plurality of memory circuits when receiving the column address and the second command and discards read data from a memory circuit that is not designated by the column address among the plurality of memory circuits.