Serially connected memory having subdivided data interface

A memory device comprising:

• n data input pins for receiving data from a first external device;
• n data output pins for transmitting data to a second external device;
• and
• internal logic selectively configurable to operate the memory device in one of a first mode and a second mode,
• when operating in the first mode, the memory device being operative to:
• receive data associated with a single operation on all n data input pins;
• and
• transmit data associated with a single operation on all n data output pins;
• and
• when operating in the second mode, the memory device being operative to concurrently:
• receive data associated with a first operation on only m of the data input pins;
• transmit data associated with the first operation on only m of the data output pins;
• receive data associated with a second operation on the remaining n-m of the data input pins;
• and
• transmit data associated with the second operation on the remaining n-m of the data output pins,
• where m is less than n.

A memory controller, comprising:

• an n-bit data interface for communicating with a plurality of serially-connected memory devices;
• and
• internal logic configurable to operate in a first mode to communicate each read and write operation to the memory devices using all n bits of the data interface;
• the memory controller being configurable in a second mode to concurrently:
• communicate data associated with a first operation to the memory devices using only m bits of the data interface, where m is less than n;
• and
• communicate data associated with a second operation to the memory devices using the remaining n-m bits of the data interface.

A method of operating a plurality of serially-connected memory devices connected by an n-bit data interface, the method comprising:

• sending a first command from a memory controller, the first command being addressed to a first target memory device;
• communicating data associated with the first command between the memory controller and the first target memory device on only m bits of the data interface;
• sending a second command from the memory controller, the second command being addressed to a second target memory device;
• and
• communicating data associated with the second command between the memory controller and the second target memory device on only the remaining n-m bits of the data interface.