Low Latency Two-Level Interrupt Controller Interface to Multi-Threaded Processor

A multi-threaded processor, comprising:

• a core;
• a level two interrupt controller;
• and
• a line coupling the core to the level two interrupt controller, wherein the core is configured to indicate to the level two interrupt controller, via the line, that the core is ready to receive a level two interrupt.

A processing system configured for reduced interrupt latency, the processing system comprising:

• a first interrupt controller coupled to a core;
• means for communicating a first interrupt and a first vector identifier from a second interrupt controller to the first interrupt controller;
• means for processing the first interrupt and the first vector identifier at the first interrupt controller;
• means for sending the processed interrupt to a thread in the core;
• means for determining when the core is ready to receive a second interrupt;
• and
• means for sending an instruction from the core to the second interrupt controller indicating the core is ready to receive the second interrupt.

A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for reducing interrupt latency time, the non-transitory computer-readable storage medium comprising:

• code for communicating a first interrupt and a first vector identifier from a second interrupt controller to a first interrupt controller;
• code for processing the first interrupt and the first vector identifier at the first interrupt controller;
• code for sending the processed interrupt from the first interrupt controller to a thread in a core;
• code for determining when the core is ready to receive a second interrupt;
• and
• code for sending an instruction from the core to the second interrupt controller indicating the core is ready to receive the second interrupt.