Interruption facility for adjunct processor queues
AssigneeInternational Business Machines Corporation
InventorsCharles W. Gainey, JR., Klaus Meissner, Damian L. Osisek, Klaus Werner
Life of this patent
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Abstract
Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.
Claims14
A method for making a computer program product for facilitating processing of queues of a processing environment, the method comprising:
- first assembling instructions for causing a computer to determine that a queue of the processing environment has transitioned from a no replies pending state to a reply pending state, wherein the queue is indirectly accessible to user programs, and wherein the no replies pending state is a state in which the queue is empty, and the reply pending state is a state in which the queue is not empty, and storing the first assembling instructions on a tangible computer storage medium;
- second assembling instructions for causing a computer to enable the queue for interruption, the enabling comprising employing a process adjunct processor queue (PQAP) instruction to enable the queue for interruption, wherein the PQAP instruction employs general registers 0, 1 and 2 for input, and general register 1 for output, and storing the second assembling instructions on a tangible computer storage medium;
- and
- third assembling instructions for causing a computer to initiate, by a processor, an interrupt for the queue, wherein the initiating is based on enabling the queue and determining that the queue has transitioned from the no replies pending state to the reply pending state, wherein the interrupt is initiated based on the queue transitioning from an empty state to a non-empty state, and the interrupt is not initiated based on the queue not transitioning from the empty state to the non-empty state, and storing the third assembling instructions on a tangible computer storage medium.
A method of manufacturing a computer system for facilitating processing of queues of a processing environment, the method comprising:
- first assembling instructions for causing a computer to determine that a queue of the processing environment has transitioned from a no replies pending state to a reply pending state, wherein the queue is indirectly accessible to user programs, and wherein the no replies pending state is a state in which the queue is empty, and the reply pending state is a state in which the queue is not empty, and storing the first assembling instructions on a tangible computer storage medium;
- second assembling instructions for causing a computer to enable the queue for interruption, the enabling comprising employing a process adjunct processor queue (PQAP) instruction to enable the queue for interruption, wherein the PQAP instruction employs general registers 0, 1 and 2 for input, and general register 1 for output, and storing the second assembling instructions on a tangible computer storage medium;
- and
- third assembling instructions for causing a computer to initiate, by a processor, an interrupt for the queue, wherein the initiating is based on enabling the queue and determining that the queue has transitioned from the no replies pending state to the reply pending state, wherein the interrupt is initiated based on the queue transitioning from an empty state to a non-empty state, and the interrupt is not initiated based on the queue not transitioning from the empty state to the non-empty state, and storing the third assembling instructions on a tangible computer storage medium.
Dependencies are inferred from the claim text.