Inter-processor communication apparatus and method
AssigneeDesignart Networks Ltd
InventorsMEIR TSADIK, ALBERT YOSHER
Life of this patent
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Abstract
Inter-processor communication (IPC) apparatus and a method for providing communication between two processors having a shared memory, the IPC apparatus including an arbitrated bus coupling the processors to one another and to the memory, a buffer in the shared memory associated with each processor, and at least one pair of First In First Out hardware units (FIFOs) coupled to each processor, the FIFOs holding pointers to addresses in the buffer associated with that processor, wherein a first of the pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty portions of the buffer while the second of the pair of FIFOs (a message FIFO) is configured to hold pointers to portions of the buffer having data therein.
Claims10
Inter-processor communication (IPC) apparatus for communication between two processors having a shared memory, the IPC apparatus comprising:
- an arbitrated bus coupling the processors to one another and to the memory;
- at least one buffer in the shared memory associated with each processor;
- and
- at least one pair of First In First Out hardware units (FIFOs) coupled to each said processor, said FIFOs holding pointers to each said at least one buffer associated with that processor;
- wherein a first of said pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty buffers associated with that processor while a second of said pair of FIFOs (a message FIFO) is configured to hold pointers to buffers associated with that processor having data therein.
A method for providing inter-processor communication between two processors having a shared memory, the method comprising:
- coupling the processors to one another and to the memory by an arbitrated bus;
- associating at least one buffer in the shared memory with each processor;
- coupling at least one pair of First In First Out hardware units (FIFOs) to each said processor, said FIFOs holding a pointer to each said at least one buffer in the memory associated with that processor;
- and
- configuring a first of said pair of FIFOs (an empty buffer FIFO) to hold pointers to empty buffers associated with that processor and configuring a second of said pair of FIFOs (a message FIFO) to hold pointers to buffers associated with that processor having data therein.
Dependencies are inferred from the claim text.