Successive approximation analog to digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) for converting an analog input into an N-bit digital output in a conversion phase composed of a plurality of conversion sub-phases, comprising:

• three comparators;
• three capacitor arrays, each having two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator;
• an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.