US 2013/0076546 A1Published application

Charge compensation calibration for high resolution data converter

AssigneeHong Kong Applied Science and Technology Research Institute Company Limited

InventorsKam Chuen WAN, Yat To (William) WONG, Ho Ming (Karen) WAN, Kwai Chi CHAN

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Abstract

A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Claims21

Dependent claims

A method for calibrating a digital-to-analog converter (DAC) comprising:

during a pre-charge phase:
grounding an X line and grounding a Y line that are inputs to a comparator;
driving a thermometer code to an upper group of binary-weighted capacitors and to a surrogate capacitor that has a same capacitance value as a smallest capacitor in the upper group, for both an X-side array that has all capacitors connected to the X line and for a Y-side array that has all capacitors connected to the Y line;
wherein the thermometer code drives a target capacitor low and drives lower capacitors high in the upper group when calibrating the target capacitor;
wherein the thermometer code also drives low any larger capacitors that have a larger capacitance value than the target capacitor;
driving low all capacitors in a lower group of binary-weighted capacitors and driving low a termination capacitor that has a same capacitance value as a smallest capacitor in the lower group, for both the X-side array and the Y-side array;
during a bottom-plate sampling phase:
floating the X line and the Y line to allow the comparator to compare X and Y-side voltages;
during an error acquisition phase:
inverting the thermometer code applied to the upper group so that the target capacitor and any larger capacitors are driven high and the lower capacitors are driven low in the X-side array;
wherein charge sharing occurs between the target capacitor and the lower capacitors connected through the X line;
continuing to drive the thermometer code to the upper group of the Y-side array;
during a calibration search phase:
driving a test sequence of high and low values onto the lower group of binary-weighted capacitors in the Y-side array;
continuing to drive low all capacitors in the lower group of binary-weighted capacitors and the termination capacitor in the X-side array;
comparing voltages on the X line and the Y line and adjusting the high and low values applied to the lower group until a minimum voltage difference is detected by the comparator;
and
storing as a calibration value for the target capacitor the high and low values applied to the lower group of the Y-side array that produced the minimum voltage difference.

15 more elements

A calibrating Analog-to-Digital Converter (ADC) comprising:

Successive-Approximation-Register (SAR) means for storing a digital value of M+N+2 significant bits;
wherein M and N are whole numbers and M is at least 4;
first analog input means for receiving a first analog voltage;
first sharing node means for generating a first compare voltage;
first upper binary-weighted capacitor array means for switching charge to the first sharing node means in response to M+1 bits of digital values from the SAR means that are applied to capacitors having capacitance values of 2i+N times C, wherein C is a minimum capacitance value and i is a whole number between 0 and M;
first upper switch means for connecting the first analog input means to capacitors in the first upper binary-weighted capacitor array means during a sampling phase, and for connecting M+1 digital values from the SAR means to capacitors in the first upper binary-weighted capacitor array means during a conversion phase after the sampling phase;
wherein the first upper binary-weighted capacitor array means further comprises two capacitors each having a lowest upper capacitance value of 2N times C but controlled by different significant bits from the SAR means;
first lower binary-weighted capacitor array means for switching charge to the first sharing node means in response to N+1 bits of digital values from the SAR means that are applied to capacitors having capacitance values of 2i times C, wherein C is a minimum capacitance value and i is a whole number between 0 and N;
first lower switch means for connecting the first analog input means to capacitors in the first lower binary-weighted capacitor array means during a sampling phase, and for connecting N+1 digital values from the SAR means to capacitors in the first binary-weighted capacitor array means during a conversion phase after the sampling phase;
wherein the first lower binary-weighted capacitor array means further comprises two capacitors each having the minimum capacitance value of C but controlled by different significant bits from the SAR means;
first grounding switch means for grounding the first sharing node means during the sampling phase;
second analog input means for receiving a second analog voltage;
second sharing node means for generating a second compare voltage;
second upper binary-weighted capacitor array means for switching charge to the second sharing node means in response to M+1 bits of digital values from the SAR means that are applied to capacitors having capacitance values of 2i+N times C, wherein C is a minimum capacitance value and i is a whole number between 0 and M;
second upper switch means for connecting the second analog input means to capacitors in the second upper binary-weighted capacitor array means during a sampling phase, and for connecting M+1 digital values from the SAR means to capacitors in the second upper binary-weighted capacitor array means during a conversion phase after the sampling phase;
wherein the second upper binary-weighted capacitor array means further comprises two capacitors each having a lowest upper capacitance value of 2N times C but controlled by different significant bits from the SAR means;
second lower binary-weighted capacitor array means for switching charge to the second sharing node means in response to N+1 bits of digital values from the SAR means that are applied to capacitors having capacitance values of 2i times C, wherein C is a minimum capacitance value and i is a whole number between 0 and N;
second lower switch means for connecting the second analog input means to capacitors in the second lower binary-weighted capacitor array means during a sampling phase, and for connecting N+1 digital values from the SAR means to capacitors in the second binary-weighted capacitor array means during a conversion phase after the sampling phase;
wherein the second lower binary-weighted capacitor array means further comprises two capacitors each having the minimum capacitance value of C but controlled by different significant bits from the SAR means;
second grounding switch means for grounding the second sharing node means during the sampling phase;
compare means for comparing the first compare voltage to the second compare voltage to generate a compare output;
and
sequencing means for adjusting the digital value stored in the SAR means in response to the compare output.

20 more elements

A calibrating converter comprising:

a first charge-sharing line;
a first grounding switch that grounds the first charge-sharing line;
a plurality of first switches;
a first array of capacitors having weighted capacitance values, wherein first array capacitors in the first array connect to the first charge-sharing line and to the plurality of first switches;
a first termination capacitor in the first array of capacitors, the first termination capacitor having a same minimum capacitance value as a minimum capacitor, wherein two capacitors in the first array of capacitors have the same minimum capacitance value;
a first surrogate capacitor in the first array of capacitors, the first surrogate capacitor having a middle capacitance and a first middle capacitor having the middle capacitance, wherein two capacitors in the first array of capacitors have the middle capacitance;
a first upper group of capacitors in the first array of capacitors, the first upper group comprising the first surrogate capacitor and all capacitors in the first array of capacitors having capacitance values greater than the middle capacitance;
a first lower group of capacitors in the first array of capacitors, the first lower group comprising the first termination capacitor and all capacitors in the first array of capacitors having capacitance values less than the middle capacitance;
a first analog input having an analog input voltage, a plurality of first digital values;
wherein the plurality of first switches connect the first analog input to the first array of capacitors during a sampling phase during normal operation;
wherein the plurality of first switches connect the first digital values to the first array of capacitors during a conversion phase after the sampling phase during normal operation;
a second charge-sharing line;
a second grounding switch that grounds the second charge-sharing line;
a plurality of second switches;
a second array of capacitors having weighted capacitance values, wherein second array capacitors in the second array connect to the second charge-sharing line and to the plurality of second switches;
a second termination capacitor in the second array of capacitors, the second termination capacitor having the same minimum capacitance value as the minimum capacitor, wherein two capacitors in the second array of capacitors have the same minimum capacitance value;
a second surrogate capacitor in the second array of capacitors, the second surrogate capacitor having the middle capacitance and a second middle capacitor having the middle capacitance, wherein two capacitors in the second array of capacitors have the middle capacitance;
a second upper group of capacitors in the second array of capacitors, the second upper group comprising the second surrogate capacitor and all capacitors in the second array of capacitors having capacitance values greater than the middle capacitance;
a second lower group of capacitors in the second array of capacitors, the second lower group comprising the second termination capacitor and all capacitors in the second array of capacitors having capacitance values less than the middle capacitance;
a second analog input having an analog input voltage,
a plurality of second digital values;
wherein the plurality of second switches connect the second analog input to the second array of capacitors during a sampling phase during normal operation;
wherein the plurality of second switches connect the second digital values to the second array of capacitors during a conversion phase after the sampling phase during normal operation;
a comparator that receives the first compare voltage and compares the first compare voltage to a second comparator input to generate a compare output;
and
control logic for adjusting the first digital values to the plurality of first switches and for adjusting the second digital values to the plurality of second switches.

23 more elements

Dependencies are inferred from the claim text.