Split decode latch with shared feedback
AssigneeLSI Corporation
InventorsRichard J. Stephani, Amy R. Rittenhouse, Donald A. Evans
Life of this patent
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Abstract
An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up.
Claims20
An apparatus comprising:
- a first circuit configured to generate an output signal in response to (i) an intermediate signal and (ii) a clock signal;
- and
- a second circuit configured to generate said intermediate signal and a digital complement of said output signal in response to (i) an input signal and (ii) said clock signal, wherein said intermediate signal forms a feedback to ensure said output signal and said digital complement of said output signal are in complementary states during a power up.
An apparatus comprising:
- a first circuit configured to generate an output signal in response to (i) a first intermediate signal, (ii) a second intermediate signal, (iii) a first clock signal and (iv) a second clock signal;
- a second circuit configured to generate said first intermediate signal in response to (i) an input signal, (ii) said first clock signal and (iii) said second clock signal;
- a third circuit configured to generate a complement of said output signal in response to (i) said first clock signal, (ii) said second clock signal and (iii) said input signal;
- and
- a fourth circuit configured to generate said second intermediate signal in response to said complement of said output signal, (ii) said first clock signal and (iii) said second clock signal.
An apparatus comprising:
- means for generating an output signal in response to (i) an intermediate signal and (ii) a clock signal;
- and
- means for generating said intermediate signal and a digital complement of said output signal in response to (i) an input signal and (ii) said clock signal, wherein said intermediate signal forms a feedback to ensure said output signal and said digital complement of said output signal are in complementary states during a power up.
Dependencies are inferred from the claim text.