Nonvolatile programmable logic switch

A nonvolatile programmable logic device comprising a plurality of wirings and a connection unit configured to switch connection/disconnection of the wirings, the connection unit comprising one or more programmable logic switches,

• each programmable logic switch comprising first and second cells,
• each of the first and second cells comprising:
• a first memory having a first terminal, a second terminal, and a third terminal which receives a control signal to control a memory state, the first memory being a first memory transistor having a gate structure formed by stacking a first insulation film, a charge trap film, a second insulation film, and a gate electrode, the source and the drain of the first memory transistor being the first and second terminal, and the gate electrode being the third terminal;
• a first transistor connected at one of source/drain thereof to the second terminal;
• and
• a second transistor connected at a gate thereof to the other of the source/drain of the first transistor,
• the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common, and
• when conducting writing into the first memory in the first cell, the third terminals being connected to a write power supply which generates a write voltage, the first terminal of the first memory in the first cell being connected to a ground power supply, and the first terminal of the first memory in the second cell being connected to a write inhibit power supply which generates a write inhibit voltage.

A nonvolatile programmable logic device comprising a plurality of wirings and a connection unit configured to switch connection/disconnection of the wirings, the connection unit comprising one or more programmable logic switches,

• each programmable logic switch comprising first and second cells,
• each of the first and second cells comprising:
• a first memory having a first terminal, a second terminal, and a third terminal which receives a control signal to control a memory state, the first memory being a first memory transistor having a gate structure formed by stacking a first insulation film, a charge trap film, a second insulation film, and a gate electrode, the source and the drain of the first memory transistor being the first and second terminal, and the gate electrode being the third terminal;
• a first transistor connected at one of source/drain thereof to the second terminal;
• a second transistor connected at a gate thereof to the other of the source/drain of the first transistor;
• and
• a second memory, the second memory comprises a fourth terminal, a fifth terminal connected to the second terminal, and a sixth terminal which receives a control signal to control a memory state, the second memory being a second memory transistor having a gate structure formed by stacking a first insulation film, a charge trap film, a second insulation film, and a gate electrode, a source and a drain of the second memory transistor being the fourth and fifth terminal, and the gate electrode being the sixth terminal,
• the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common, the sixth terminal of the second memory in the first cell and the sixth terminal of the second memory in the second cell being connected in common and
• when conducting writing into the first memory in the first cell, the third terminals being connected to a write power supply which generates a write voltage, the first terminal of the first memory in the first cell being connected to a ground power supply, and the first terminal of the first memory in the second cell being connected to a write inhibit power supply which generates a write inhibit voltage.