Programmable Logic Sensing in Magnetic Random Access Memory
AssigneeQUALCOMM Incorporated
InventorsJung Pill Kim, Tae Hyun Kim, Wenqing Wu, Xiaochun Zhu, Seung H. Kang
Life of this patent
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Abstract
A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
Claims14
A programmable logic circuit, comprising:
- a plurality of magnetic tunnel junctions (MTJs) configurable as logic circuitry including a first category of logic gates and a second category of logic gates;
- and
- reference circuitry configurable to select a first reference level for the first category of logic gates and a second reference level for the second category of logic gates.
A method of magnetic random access memory (MRAM) logic sensing, comprising:
- coupling an output node of an MRAM logic gate to a reference node of a reference circuit of the MRAM, the MRAM logic gate in one of at least two categories of logic gates;
- and
- configuring the reference circuit to provide one of at least two reference levels corresponding to the one of at least two categories of logic gates.
A method of magnetic random access memory (MRAM) logic sensing, comprising the steps of:
- coupling an output node of an MRAM logic gate to a reference node of a reference circuit of the MRAM, the MRAM logic gate in one of at least two categories of logic gates;
- and
- configuring the reference circuit to provide one of at least two reference levels corresponding to the one of at least two categories of logic gates.
An apparatus for magnetic random access memory (MRAM) logic sensing, comprising:
- means for coupling an output node of an MRAM logic gate to a reference node of a reference circuit of the MRAM, the MRAM logic gate in one of at least two categories of logic gates;
- and
- means for configuring the reference circuit to provide one of at least two reference levels corresponding to the one of at least two categories of logic gates.
Dependencies are inferred from the claim text.