Transistor array for testing
AssigneeUnited Microelectronics Corp.
InventorsHSIN-MING HOU, JI-FU KUNG
Life of this patent
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Abstract
A transistor array for testing is provided. The transistor array includes a plurality of tested units. Each of the tested unit includes a tested transistor and a first to third switches. The tested transistor has a control terminal, a first and a second terminals and a bulk. The first switch is coupled between the first terminal and a leakage transporting line. The second switch is coupled between the second terminal and the leakage transporting line. The third switch is coupled between the control terminal and a bias providing line. The first to third switches are turned on or turned off according to a control signal. When the tested transistor is selected to be tested, the first to third switches are turned on according to the control signal.
Claims11
A transistor array for testing, comprising:
- a plurality of tested units, each of the tested units comprising:
- a tested transistor, having a control terminal, a first terminal, a second terminal and a bulk;
- a first switch, coupled between the first terminal of the tested transistor and a leakage transporting line;
- a second switch, coupled between the second terminal of the tested transistor and the leakage transporting line;
- and
- a third switch, coupled between the control terminal of the tested transistor and a bias providing line,
- wherein the first, the second and the third switches are turned on or turned off according to a control signal, and when the tested transistor is not selected, the first, the second and the third switches are turned on according to the control signal.
Dependencies are inferred from the claim text.