Semiconductor Test Structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAn-Chun Tu, Chen-Ming Huang, Chih-Jen Wu, Chin-Hsiang Lin
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Abstract
A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.
Claims20
A resistive test structure comprising:
- a semiconductor substrate with an active region;
- a gate stack formed over the active region;
- a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack;
- and
- a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.
A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising:
- performing one or more processes to form the resistive device;
- measuring a resistance between the electrical contacts;
- and
- correlating the measured resistance with a variation in one or more of the processes.
A semiconductor device comprising:
- a Metal Oxide Semiconductor (MOS) structure having:
- a semiconductor substrate with an active region and a gate stack disposed on the active region;
- a first pair of electrical contacts on opposing side of the gate stack in communication with the active region, the first pair of electrical contacts being electrically connected across a first dimension of the gate stack;
- and
- a second pair of electrical contacts on the opposing side of the gate stack in communication with the active region, the second pair of electrical contacts being electrically connected across the first dimension of the gate stack, the first and second pairs of electrical contacts spaced along a longest dimension of the gate stack perpendicular to the first dimension.
Dependencies are inferred from the claim text.