US 2013/0076329 A1Published application

Equalization circuit and equalization system

AssigneeIPGoal Microelectronics (SiChuan) Co., Ltd.

InventorsZhaolei Wu, Lei Li

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Abstract

An equalization circuit, includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit, a second regulating circuit, and a bias voltage generating circuit. The bias voltage generating circuit is connected with both the first regulating circuit and the second regulating circuit. The first regulating circuit includes a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a first resistor connected with the first FET, a second resistor connected with the second FET, a third resistor connected with the third FET, a fourth resistor connected with the fourth FET, a fifth resistor connected with the third FET, a sixth resistor connected with the fourth FET, a first capacitor connected with the third FET, and a second capacitor connected with the fourth FET. An equalization system is further provided.

Claims10

Dependent claims

An equalization circuit, comprising a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit connected with said first input terminal and said second input terminal for regulating a frequency-amplitude characteristic of input signals at said first input terminal and said second input terminal, a second regulating circuit connected with said first regulating circuit, said first output terminal and said second output terminal, and a bias voltage generating circuit, wherein said bias voltage generating circuit is respectively connected with said first regulating circuit and said second regulating circuit, said first regulating circuit comprises a first field effect transistor (FET) connected with said second input terminal, a second FET connected with said first FET, a third FET, a fourth FET connected with said third FET, a first resistor connected with said first FET, a second resistor connected with said second FET, a third resistor connected with said third FET, a fourth resistor connected with said fourth FET, a fifth resistor connected with said third FET and said third resistor, a sixth resistor connected with said fourth FET and said fourth resistor, a first capacitor connected with said third FET and said fifth resistor, and a second capacitor connected with said fourth FET and said sixth resistor.

An equalization system, comprising a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit connected with said first input terminal and said second input terminal for regulating a frequency-amplitude characteristic of differential signals at said first input terminal and said second input terminal, a second regulating circuit connected with said first regulating circuit for obtaining an appropriate regulating range of a transmission signal, and a bias voltage generating circuit for providing a constant current for said equalization system to work normally, wherein said bias voltage generating circuit is respectively connected with said first regulating circuit and said second regulating circuit.

Dependencies are inferred from the claim text.