Package-on-package system with through vias and method of manufacture thereof
AssigneeSTATS ChipPAC, Ltd.
InventorsDongSam Park, JoungIn Yang
Life of this patent
Estimating the term…
Abstract
A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.
Claims20
A method of manufacture of a package-on-package system comprising:
- providing a substrate connection;
- attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive;
- forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface;
- and
- creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.
A method of manufacture of a package-on-package system comprising:
- providing a package substrate including a package carrier and a substrate connection;
- attaching a semiconductor die to the package substrate with an adhesive, with the adhesive directly contacting the substrate connection;
- connecting the semiconductor die to the substrate connections in the package substrate using electrical interconnects;
- molding an encapsulant around the semiconductor die using a mold with pins to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface, wherein the pins define through openings extending from the top exposed surface through the bottom exposed surface;
- removing the package carrier of the package substrate;
- and
- creating through vias by applying solder through a stencil plate with openings aligned to the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.
A package-on-package system comprising:
- a substrate connection;
- an adhesive over the substrate connection;
- a semiconductor die attached to the substrate connection with the adhesive;
- an encapsulant surrounding at least portions of the package substrate and the semiconductor die, the encapsulant having a bottom exposed surface coplanar with a bottom surface of the substrate connection and a top exposed surface;
- and
- through vias extending from the top exposed surface to a bottom exposed surface of the encapsulant, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.
Dependencies are inferred from the claim text.