Interconnection Between Integrated Circuit and Package
AssigneeBroadcom Corporation
InventorMengzhi PANG
Life of this patent
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Abstract
In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the present invention provides a pressure distribution pedestal upon which a narrower copper pillar is disposed. A solder mini-bump is disposed on the upper exposed portion of the copper pillar, wherein the solder is softer than the copper pillar. The radius of the copper pillars is selected such that lateral deformation of the solder mini-bumps during final assembly does not form undesired conductive bridges between adjacent pillars.
Claims15
A method of forming a bump structure, comprising:
- providing a wafer, the wafer having a topside passivation layer with a plurality of openings therein to expose a corresponding plurality of bonds pads;
- disposing a first hard-mask layer over the wafer such that the first hard-mask layer covers the topside passivation layer and the bond pads;
- patterning the first hard-mask layer to form a plurality of trench openings, each trench opening exposing at least a portion of a bond pad;
- forming a base structure in each of the trenches in the first hard-mask layer, each base structure having an exposed top surface;
- disposing a second hard-mask layer over the wafer such that the second hard-mask layer covers the first hard-mask layer and the exposed surface of each base structure;
- patterning the second hard-mask layer to form a plurality of trench openings, each trench opening exposing at least a portion of at least one of the base structures;
- forming a pillar structure in each of the trenches in the second hard-mask layer, each pillar structure having an exposed top surface;
- and
- disposing a solder cap on the exposed surface of at least one pillar structure.
A method of producing an interconnection structure, comprising:
- forming a base trench superjacent a bond pad, the bond pad disposed on a wafer;
- forming an electrically conductive base having dimensions substantially defined by the base trench, the base electrically connected to the bond pad;
- forming a pillar trench superjacent the base;
- forming an electrically conductive pillar having dimensions substantially defined by the pillar trench, the pillar electrically connected to the base;
- and
- forming a solder cap on an exposed surface of the pillar;
- wherein the cross sectional area of the pillar, taken in a plane parallel to the wafer, is less than the cross sectional area of the base, taken in a plane parallel to the wafer.
A method of assembly, comprising:
- providing an integrated circuit having a plurality of bond pads, each bond pad having a force-redistributing base structure disposed thereon, each force-redistributing base structure having a first cross-sectional area, each force-redistributing base structure having a pillar disposed thereon, each pillar having a second cross-sectional area, each pillar having a solder cap disposed thereon;
- aligning at least two solder caps to a corresponding two connection terminals on a substrate;
- positioning the integrated circuit and the substrate relative to each other such that the solder caps and connection terminals are in contact with each other;
- and
- forming a soldered connection between the pillars of the integrated circuit and the connection terminals of the substrate;
- wherein the each force-redistributing base structure is electrically connected to the bond pad upon which it is disposed;
- each pillar is electrically connected to the pedestal upon which it is disposed, and the second cross-sectional area is less than the first cross-sectional area.
The method of claim 16, wherein the force-redistributing base structures comprise Cu and the pillars comprise Cu.
The method of claim 16, wherein the substrate is selected from the group consisting of a printed circuit board, a ceramic substrate, an interposer, a chip package, a bond pad interface of a chip, and a through-silicon-via interface of a chip.
An electronic product, comprising:
- an integrated circuit having a plurality of bond pads, each bond pad having a force-redistributing base structure disposed thereon and electrically connected thereto, each force-redistributing base structure having a first cross-sectional area, each force-redistributing base structure having a pillar disposed thereon and electrically connected thereto, each pillar having a second cross-sectional area, wherein the second cross-sectional area is less than the first cross-sectional area and wherein the pillars have a predetermined spaced apart relationship to each other;
- and
- a substrate having a plurality of connection terminals, the plurality of connection terminals having a spaced apart relationship to each other, and the spaced apart relationship of the connection terminals corresponds to the predetermined spaced apart relationship of the pillars;
- wherein the pillars and the connection terminals are electrically coupled to each other.
The electronic product of claim 20, wherein the force-redistributing base structure comprises copper, the pillar comprises copper, and the electrical coupling between corresponding pillars and connection terminals is formed by solder.
Dependencies are inferred from the claim text.