Method for Three Dimensional Integrated Circuit Fabrication

A method comprising:

• providing a stack wherein a plurality of semiconductor dies are mounted on a first side of a wafer, wherein the wafer comprises a plurality of through vias;
• forming a molding compound layer on the first side of the wafer, wherein the plurality of semiconductor dies are embedded in the first molding compound layer;
• extending the molding compound layer covering an outer edge of the wafer;
• thinning a second side of the wafer to expose the plurality of through vias;
• attaching the stack to a tape frame;
• and
• dicing the stack to separate the stack into a plurality of individual packages.

A structure comprising:

• a substrate;
• and
• a stack mounted on the substrate comprising:
• a plurality of semiconductor dies bonded on a first side of a die;
• and
• a molding compound layer formed on the first side of the die and covering an outer edge of the die, wherein the plurality of semiconductor dies are embedded in the molding compound layer.