Semiconductor package with high-side and low-side mosfets and manufacturing method
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsYuPing Gong, Yan Xun Xue, Liang Zhao
Life of this patent
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Abstract
A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.
Claims19
A semiconductor package including co-packaged high-side (HS) and low-side (LS) semiconductor chips, comprising:
- a conductive lead frame comprising a die paddle;
- a LS semiconductor chip comprising a top source, a top gate and a bottom drain;
- a HS semiconductor chip comprising a top source, a top gate and a bottom drain, wherein a plurality of conductive source balls are formed on its top source and a plurality of conductive gate balls are formed on its top gate,
- wherein the LS semiconductor chip is connected to a front surface of the lead frame with bottom drain of the LS semiconductor chip electrically connected to a top surface of the die paddle, and wherein the HS semiconductor chip is connected to a back surface of the lead frame with top source of the HS semiconductor chip electrically connected to a bottom surface of the die paddle through the plurality of conductive source balls;
- and
- a package body encapsulating the LS semiconductor chip, the die paddle of lead frame, and a HS semiconductor chip, wherein the backside of the HS semiconductor chip is exposed out of the package body.
A manufacturing method of a semiconductor package including co-packaged HS and LS semiconductor chips, the method comprises the following steps:
- providing a lead frame made of conductive materials, the lead frame comprises a die paddle;
- forming a plurality of LS semiconductor chips on a first semiconductor wafer, wherein each LS semiconductor chip comprises a top source and a top gate on a front side of the first semiconductor wafer and a bottom drain on a backside of the semiconductor wafer;
- and singulating individual LS semiconductor chips from the first semiconductor wafer;
- forming a plurality of HS semiconductor chips on a second semiconductor wafer, wherein each HS semiconductor chip comprises a top source and a top gate on a front side of the second semiconductor wafer and a bottom drain on a backside of the second semiconductor wafer;
- depositing a plurality of conductive source balls and conductive gate balls on top source and top gate of the HS semiconductor chip correspondingly;
- and singulating the individual HS semiconductor chips from the second semiconductor wafer;
- attaching the LS semiconductor chip on the front side of the lead frame to electrically connect its bottom drain on a top surface of the die paddle;
- flipping over the lead frame and flipping and attaching the HS semiconductor chip on the backside of lead frame to electrically connect its top source to the bottom surface of the die paddle through the plurality of conductive source balls and thus to electrically connect its top source to the bottom drain of the LS semiconductor chip;
- encapsulating the LS semiconductor chip, the die paddle of the lead frame, and the HS semiconductor chip with a molding compound forming the semiconductor package, wherein the backside of the HS semiconductor chip is exposed from a backside of the semiconductor package for electrical connection between its bottom drain and external devices and for heat dissipation;
- and
- separating individual semiconductor packages from the lead frame.
Dependencies are inferred from the claim text.