US 2013/0075866 A1Published application

Semiconductor device

AssigneeSemiconductor Components Industries, LLC

InventorsSeiji Otake, Yasuhiro Takeda, Yuta Miyamoto

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Abstract

A PN junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N− type epitaxial layer and be connected to an anode electrode. An N+ type diffusion layer and a P+ type diffusion layer connected to and surrounding the N+ type diffusion layer are formed in the N− type epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and the P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as the emitter, the N− type epitaxial layer as the base, and the P+ type drawing layer etc as the collector.

Claims10

Dependent claims

A semiconductor device comprising:

a semiconductor substrate of a first general conductivity type;
an epitaxial layer of a second general conductivity type formed on the semiconductor substrate;
a first buried layer of the second general conductivity type formed between the semiconductor substrate and the epitaxial layer;
a second buried layer of the first general conductivity type connected to a peripheral edge region of the first buried layer and extending from inside the semiconductor substrate into the epitaxial layer;
a drawing layer of the first general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be connected to the second buried layer;
a first diffusion layer of the second general conductivity type extending from a surface portion of the epitaxial layer into the epitaxial layer so as to be surrounded by the second buried layer and the drawing layer in plan view of the semiconductor substrate, the first buried layer covering a bottom portion of the first diffusion layer;
a second diffusion layer of the first general conductivity type connected to and surrounding the first diffusion layer in the plan view;
a cathode electrode connected to the first diffusion layer and the second diffusion layer;
and
an anode electrode connected to the drawing layer,
wherein the first buried layer and the second buried layer are configured to form a PN junction diode,
the second diffusion layer, the epitaxial layer and the drawing layer are configured to form a parasitic bipolar transistor, and
the PN junction diode and the parasitic bipolar transistor are configured to form an ESD protection element.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/612,357Filed 12 Sep 2012
Priority: JP 2011-21019827 Sep 2011
Published: 28 Mar 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 89/60
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated devices comprising arrangements for electrical or thermal…
H10D 84/611
Characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs: combinations of…
H10D 89/601
Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]:…
H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements