3D Semiconductor Device and Method of Manufacturing Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Lin Lee, Feng Yuan, Chih Chieh Yeh, Clement Hsingjen Wann
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Abstract
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.
Claims20
A semiconductor device comprising:
- a substrate;
- a 3D structure disposed over the substrate;
- a dielectric layer disposed over the 3D structure;
- a work function metal group (WFMG) layer disposed over the dielectric layer;
- and
- a gate structure disposed over the WFMG layer,
- wherein the gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure, the source and drain region defining a channel region therebetween, and
- wherein the gate structure induces a stress in the channel region.
A method of manufacturing, comprising:
- providing a substrate;
- forming a 3D structure over the substrate;
- forming a dielectric layer over a portion of the 3D structure;
- forming a work function metal group (WFMG) layer over the dielectric layer;
- forming a gate structure over the WFMG layer, the gate structure separating a source region and a drain region of the 3D structure, wherein the source and drain region define a channel region therebetween;
- and
- performing a reaction process on the gate structure, wherein responsive to the reaction process a volume of the gate structure changes.
A method of manufacturing a FinFET device comprising:
- providing a semiconductor substrate;
- forming a fin structure over the semiconductor substrate;
- forming a dielectric layer over a portion of the fin structure;
- forming a work function metal group (WFMG) layer over the dielectric layer;
- forming a gate structure including Poly-Si over the WFMG layer, wherein the gate structure traverses the fin structure, and wherein the gate structure separates a source region and a drain region of the fin structure, the source and drain region defining a channel region therebetween;
- forming a metal layer over the gate structure;
- annealing the gate structure including Poly-Si and the metal layer such that the metal layer is able to react with Poly-Si of the gate structure to form silicide;
- and
- responsive to the annealing a volume of the gate structure changes such that a stress is induced in the channel region.
Dependencies are inferred from the claim text.