# US 2013/0075810 A1 · Semiconductor power devices integrated with a trenched clamp diode

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0075810 A1
- Document ID: US20130075810A1
- Status: Published application
- Kind: A1
- Application number: 13/246,367
- Filed: 2011-09-27
- Published: 2013-03-28
- Earliest claimed: 2011-09-27
- Assignees: Force Mos Technology Co., Ltd.
- Inventors: Fu-Yuan HSIEH
- Web page: https://patentgrep.com/patent/US20130075810A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 8/25: Zener diodes
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes}
- H10D 89/611: {using diodes as protective elements}
- H10D 1/47: Resistors having no potential barriers
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D 64/232: {Emitter electrodes for IGBTs}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor power device having shielded gate structure integrated with a trenched clamp diode formed in a semiconductor silicon layer, wherein the shielded gate structure comprises a shielded electrode formed by a first poly-silicon layer and a gate electrode formed by a second poly-silicon layer. The trenched clamp diode is formed by the first poly-silicon layer. A shielded gate mask used to define the shielded gate is also used to define the trenched clamp diode. Therefore, one poly-silicon layer and a mask for the trenched clamp diode are saved.

## Claims

### Claim 1

A semiconductor power device integrated with a trenched clamp diode comprising;
a plurality of a first type trenches extending into a semiconductor silicon layer, surrounded by source regions of a first conductivity type encompassed in body regions of a second conductivity type in a active area; and
a trenched clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of said first conductivity type next to doped regions of said second conductivity type, formed in a second type trench as a clamp diode trench extending into said semiconductor silicon layer.

### Claim 2 (depends on 1)

The semiconductor power device of claim 1 further comprises:
each of said first type gate trenches being filled with a shielded electrode in a lower portion and a gate electrode in an upper portion of said first type gate trenches wherein said source regions surrounding around said gate electrode, and said body regions disposed at a level above a bottom of said gate electrode;
said shielded electrode formed by a first poly-silicon being insulated from said semiconductor silicon layer by a first gate insulation layer and said gate electrode formed by a second poly-silicon being insulated from said semiconductor silicon layer by a second gate insulation layer;
said shielded electrode being insulated from said gate electrode by an inter-electrode insulation layer;
said trenched clamp diode being formed by said first poly-silicon layer and being insulated from said semiconductor silicon layer by said first insulation layer; and
a plurality of trenched source-body contacts penetrating through a contact interlayer, said source regions and extending into said body regions between adjacent said first type gate trenches filled with a contact metal plug and connected to a source metal layer of said semiconductor power device.

### Claim 3 (depends on 2)

The semiconductor power device of claim 2, wherein:
said source regions have a doping concentration along trench sidewalls of said trenched source-body contact higher than along an adjacent channel region near said first type gate trenches at a same distance from a top surface of said semiconductor silicon layer, said source regions have a junction depth along the trench sidewalls of said trenched source-body contact greater than along said adjacent channel region, and said source regions have a doping profile of a Gaussian-distribution along the top surface of said semiconductor silicon layer from the trench sidewalls of said trenched source-body contact to said adjacent channel region.

### Claim 4 (depends on 2)

The semiconductor power device of claim 2, wherein:
said source regions have a same doping concentration at a same distance from a top surface of said semiconductor silicon layer, and said source regions have a same junction depth from the top surface of said semiconductor silicon layer.

### Claim 5 (depends on 2)

The semiconductor power device of claim 2 further comprises:
a body contact doped region of said second conductivity type formed in said body regions and having a higher doping concentration than said body regions, wherein said body contact doped region is underneath said source regions and surrounding at least a bottom of said trenched source-body contact to reduce the contact resistance between said body regions and said contact metal plug in said trenched source-body contact.

### Claim 6 (depends on 2)

The semiconductor power device of claim 2, wherein said contact metal plug is tungsten metal plug padded by a barrier metal layer, and has a top surface no higher than said contact interlayer.

### Claim 7 (depends on 2)

The semiconductor power device of claim 2, wherein said contact metal plug is tungsten metal plug padded by a barrier layer, and is extending over said contact interlayer.

### Claim 8 (depends on 2)

The semiconductor power device of claim 2 further comprises:
a third type trenches extending into said semiconductor silicon layer filled with a single shielded electrode formed by a first poly-silicon layer and insulated from said semiconductor silicon layer by said first gate insulation layer, wherein said single shielded electrode is connected to a source metal layer via a trenched shielded electrode contacts in said shielded electrode, filled with a contact metal plug;
a fourth type trenches extending into said semiconductor silicon layer, filled with a shielded electrode and a gate electrode above, wherein said gate electrode in said fourth type gate trench is connected to a gate metal layer of said semiconductor power device via trenched gate contacts in said gate electrode, filled with a contact metal plug; and
trenched clamp diode contacts filled with said contact metal plug and extending into said doped regions of said first conductivity type on two opposite sides of said trenched clamp diode.

### Claim 9 (depends on 8)

The semiconductor power device of claim 8 further comprises a termination area comprises multiple trenched floating gates in a fifth type trenches formed in said semiconductor silicon layer and spaced from each other, wherein each of said fifth type gate trenches are filled with a single electrode formed by a first poly-silicon layer, and insulated from said semiconductor silicon layer by a first gate insulation layer.

### Claim 10 (depends on 8)

The semiconductor power device of claim 8 further comprises a termination area comprises multiple trenched floating gates in a fifth type gate trenches formed in said semiconductor silicon layer and spaced from each other, wherein each of said fifth type gate trenches is filled with a shielded electrode and a gate electrode above padded by said first and said second insulation layer, respectively.

### Claim 11 (depends on 1)

The semiconductor power device of claim 1 further comprises a trenched resistor formed by a doped poly-silicon extends into said semiconductor silicon layer.

### Claim 12 (depends on 11)

The semiconductor power device of claim 11, wherein said doped poly-silicon layer has said first conductivity type.

### Claim 13 (depends on 11)

The semiconductor power device of claim 11, wherein said doped poly-silicon layer has said second conductivity type.

### Claim 14 (depends on 1)

The semiconductor power device of claim 1, wherein said semiconductor silicon layer comprises an epitaxial layer of said first conductivity type extending over a substrate of said first conductivity type.

### Claim 15 (depends on 1)

The semiconductor power device of claim 1, wherein said semiconductor silicon layer comprises an epitaxial layer of said first conductivity type onto a buffer layer of said first conductivity type which is extending over a substrate of said second conductivity type.