Semiconductor power device with embedded diodes and resistors using reduced mask processes

A trench semiconductor power device integrated with a Gate-Drain clamp diode for Drain-Source avalanche protection wherein:

• said trench semiconductor power device comprising:
• a plurality of first type trenched gates formed in a semiconductor silicon layer;
• a first drain region of a first conductivity type formed in top portion of said semiconductor silicon layer in termination area connected to a front side drain metal layer;
• a second drain region formed on backside of said semiconductor silicon layer connected to a backside metal layer;
• said Gate-Drain clamp diode comprising:
• multiple back to back poly-silicon Zener diodes with alternating doped regions of said first conductivity type next to a second conductivity type;
• a plurality of trenched Gate-Drain clamp diode contacts extending into all of said doped regions of said first conductivity type of said Gate-Drain clamp diodes and being filled with a contact metal pug padded by a barrier metal layer;
• and
• said Gate-Drain clamp diode being connected to a first gate metal layer on one side, and connected to said drain metal layer on another side.

A trench semiconductor power device integrated with a Gate-Source clamp diode for ESD protection and a Gate-Drain clamp diode for Drain-Source avalanche protection, wherein:

• said trench semiconductor power device comprising:
• a plurality of first type trenched gates formed in a semiconductor silicon layer;
• source regions of a first conductivity type encompassed in body regions of a second conductivity type between adjacent said first type trenched gates, said source regions being connected to a source metal layer of said trench MOSFET;
• a first drain region of said first conductivity type formed in top portion of said semiconductor silicon layer in termination area connected to a front side drain metal layer;
• a second drain region formed on backside of said semiconductor silicon layer connected to a backside metal layer;
• said Gate-Source clamp diode comprising:
• multiple Gate-source Zener diodes with alternating doped regions of said first conductivity type next to a second conductivity type;
• and
• a plurality of trenched Gate-Source clamp diode contacts extending into all of said doped regions of said first conductivity type of said Gate-Source clamp diode, and being filled with a contact metal pug padded by a barrier metal layer;
• said Gate-Drain clamp diode comprising:
• multiple Gate-Drain Zener diodes with alternating doped regions of said first conductivity type next to a second conductivity type;
• and
• a plurality of trenched Gate-Drain clamp diode contacts extending into all of said doped regions of said first conductivity type of said Gate-Drain clamp diodes and being filled with said contact metal plug padded by said barrier metal layer.

A method of forming a semiconductor device integrated with at least a clamp diode comprising following steps to form a plurality of source regions of said semiconductor device and multiple first doped regions of a first conductivity type of said clamp diode simultaneously through a contact mask:

• after forming a plurality of body regions of a second conductivity type, depositing an un-doped poly-silicon layer;
• implanting said un-doped poly-silicon layer with a dopant of said second conductivity type to form a first doped region of said clamp diode;
• applying a clamp diode mask, and carrying out dry poly-silicon etching to form the clamp diode area;
• depositing a contact insulation layer;
• applying the contact mask and following with a dry oxide etching to form contact open areas in said body regions and said first doped region of said second conductivity type of said clamp diode;
• implanting said body regions of said semiconductor device and said second doped region of said clamp diode in said contact open areas with a source dopant of said first conductivity type through said contact open areas;
• diffusing said source dopant to form said source regions and said second doped regions of said first conductivity of said clamp diode in said contact open areas;

A method for manufacturing a trench semiconductor power device with embedded clamp diodes comprising sequential steps:

• forming a plurality of trenched gates in an epitaxial layer of a first conductivity type;
• forming a plurality of body regions of a second conductivity type;
• depositing a thick insulation layer over said trenched gates and said body regions;
• depositing an un-doped poly-silicon layer on said thick insulation layer;
• forming a first doped region of said second conductivity type on said un-doped poly-silicon layer by ion implant;
• applying a clamp diode mask, and carrying out a dry poly-silicon etching to form a clamp diode area;
• depositing a contact insulation layer;
• applying a contact mask and dry oxide etching to form contact open areas in said body regions and said first doped region of said second conductivity type of said clamp diode;
• implanting said body regions of said semiconductor device and said first doped region of said clamp diode with a source dopant of said first conductivity type through said contact open areas;
• diffusing said source dopant to form said source regions and said second doped regions of said first conductivity of said clamp diode in said contact open areas;
• carrying out a dry silicon etch to form a plurality of trenched source-body contacts penetrating through said source regions and extending into said body region, and to form multiple trenched clamp diode contacts in said clamp diode;
• carrying out a body contact implant followed by a RTA to form a body contact region of said second conductivity type at least around bottom of said trench source-body contacts, having doping concentration higher than said body regions;
• and
• filling said trenched source-body contacts and trenched clamp diode contacts with a Tungsten layer over a barrier metal layer.