Self-adjusted capacitive structure
AssigneeInfineon Technologies Austria AG
InventorsHans Weber, Roman Knoefler, Kurt Sorschag
Life of this patent
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Abstract
A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer.
Claims25
A method for producing a capacitive structure in a semiconductor body, comprising:
- forming a first trench in a first surface of the semiconductor body;
- forming a first dielectric layer on sidewalls and a bottom of the first trench;
- forming a first electrode layer on the first dielectric layer;
- forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap;
- forming a second dielectric layer on sidewalls and a bottom of the at least one second trench;
- and
- forming a second electrode layer on the second dielectric layer.
A method for forming a multi-level capacitive structure, comprising:
- forming a 1st level capacitive structure in a semiconductor body, the 1st level capacitive structure comprising a first trench, a first dielectric layer on sidewalls and a bottom of the first trench and a first electrode layer on the first dielectric layer;
- and
- forming at least one 2nd level capacitive structure in the semiconductor body, the at least one 2nd level capacitive structure comprising a second trench adjusted to one sidewall of the first trench, a first dielectric layer on sidewalls and a bottom of the second trench and a second electrode layer arranged on the second dielectric layer.
A multi-level capacitive structure, comprising:
- a 1st level capacitive structure in a semiconductor body, the 1st level capacitive structure comprising a first trench, a first dielectric layer on sidewalls and a bottom of the first trench and a first electrode layer on the first dielectric layer;
- and
- at least one 2nd level capacitive structure in the semiconductor body, the at least one 2nd level capacitive structure comprising a second trench adjusted to one sidewall of the first trench, a first dielectric layer on sidewalls and a bottom of the second trench and a second electrode layer on the second dielectric layer.
A transistor device, comprising:
- a drain region, a source region, a body region and a drift region arranged in a semiconductor body, the body region arranged between the source region and the drift region, and the drift region arranged between the body region and the drain region;
- a gate structure comprising a gate electrode arranged adjacent the body region, and a gate dielectric arranged between the gate electrode and the body region;
- a drift control region arranged adjacent the drift region in a lateral direction of the semiconductor body, and a drift control region dielectric arranged between the drift control region and the drift region and extending in a vertical direction of the semiconductor body;
- a capacitive element electrically coupled to the drift control region;
- and
- a multi-level capacitive structure in the semiconductor body that is self-adjusted to the drift control region dielectric and forms part of at least one of the gate structure and the capacitive element.
Dependencies are inferred from the claim text.