Semiconductor device and fabrication method
AssigneeFujitsu Limited
InventorShuichi TOMABECHI
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Abstract
A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer.
Claims18
A method for fabricating a semiconductor device, the method comprising:
- sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate;
- forming a dielectric layer having an opening after the forming of the semiconductor cap layer;
- forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer;
- and
- forming a gate electrode on the third semiconductor layer.
A method for fabricating a semiconductor device, the method comprising:
- sequentially forming a first semiconductor layer and a second semiconductor layer on a substrate;
- forming a dielectric layer having an opening after the forming of the second semiconductor layer;
- forming a third semiconductor layer containing a p-type impurity element on the second semiconductor layer exposed from the opening of the dielectric layer;
- and
- forming a gate electrode on the third semiconductor layer.
A semiconductor device comprising:
- a first semiconductor layer formed on a substrate;
- a second semiconductor layer formed on the first semiconductor layer;
- a semiconductor cap layer formed on the second semiconductor layer;
- a third semiconductor layer formed in a first region of the semiconductor cap layer;
- a gate electrode formed on the third semiconductor layer, the third semiconductor layer being formed in the first region of the semiconductor cap layer located beneath the gate electrode;
- and
- a source electrode and a drain electrode formed such that the source electrode and the drain electrode come in contact with the second semiconductor layer or the semiconductor cap layer, wherein
- the semiconductor cap layer and the third semiconductor layer are formed by doping a p-type impurity element to a semiconductor material, and
- the third semiconductor layer is a p-type semiconductor layer.
Dependencies are inferred from the claim text.