US 2013/0075758 A1Published application

Semiconductor device and method for manufacturing semiconductor device

AssigneeSumitomo Electric Industries, Ltd.

InventorsTakeyoshi MASUDA, Keiji WADA, Toru HIYOSHI

Life of this patent

Estimating the term…

Loading patent…

Abstract

A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.

Claims10

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate having a trench formed in one main surface;
a first insulating film arranged on and in contact with a wall surface of said trench;
a gate electrode arranged on and in contact with said first insulating film;
and
a first interconnection arranged on said one main surface,
said semiconductor substrate including
a drift layer having a first conductivity type, and
a body layer having a second conductivity type, which is arranged on a side of said one main surface when viewed from said drift layer,
said trench being formed to penetrate said body layer and to reach said drift layer,
said trench including an outer peripheral trench arranged to surround an active region when viewed two-dimensionally,
a potential fixing region where said body layer is exposed being formed in said one main surface opposite to said active region when viewed from said outer peripheral trench,
said first interconnection being arranged to lie over said active region when viewed two-dimensionally, and
said potential fixing region being electrically connected to said first interconnection.

10 more elements

A method of manufacturing a semiconductor device, comprising the steps of:

preparing a semiconductor substrate including a drift layer having a first conductivity type and a body layer having a second conductivity type, which is formed on said drift layer to include one main surface;
forming a trench to open on a side of said one main surface and to penetrate said body layer and reach said drift layer;
forming a first insulating film to include a wall surface of said trench;
forming a gate electrode to be in contact with said first insulating film;
and
forming a first interconnection on said one main surface,
in said step of forming a trench, an outer peripheral trench arranged to surround an active region when viewed two-dimensionally being formed, and
in said step of forming a first interconnection, said first interconnection being formed to lie over said active region when viewed two-dimensionally and to electrically be connected to a potential fixing region which is said body layer exposed at said one main surface opposite to said active region when viewed from said outer peripheral trench.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/613,801Filed 13 Sep 2012
Priority: JP 2011-20843826 Sep 2011
Published: 28 Mar 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures
H10D 62/106
By having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination…