Semiconductor device and method of manufacturing the same
AssigneeFujitsu Limited
InventorJunji KOTANI
Life of this patent
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Abstract
A semiconductor device includes: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer, wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element; and the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.
Claims20
A semiconductor device comprising:
- a first semiconductor layer formed on a substrate;
- a second semiconductor layer formed on the first semiconductor layer;
- a third semiconductor layer formed on the second semiconductor layer;
- a gate electrode formed on the third semiconductor layer;
- and
- a source electrode and a drain electrode formed in contact with the second semiconductor layer,
- wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element;
- and
- the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.
A power supply comprising the semiconductor device,
- wherein a semiconductor device includes:
- a first semiconductor layer formed on a substrate;
- a second semiconductor layer formed on the first semiconductor layer;
- a third semiconductor layer formed on the second semiconductor layer;
- a gate electrode formed on the third semiconductor layer;
- and
- a source electrode and a drain electrode formed in contact with the second semiconductor layer,
- wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element;
- and
- the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.
An amplifier comprising the semiconductor device,
- wherein a semiconductor device includes:
- a first semiconductor layer formed on a substrate;
- a second semiconductor layer formed on the first semiconductor layer;
- a third semiconductor layer formed on the second semiconductor layer;
- a gate electrode formed on the third semiconductor layer;
- and
- a source electrode and a drain electrode formed in contact with the second semiconductor layer,
- wherein a semiconductor material of the third semiconductor layer is doped with a p-type impurity element;
- and
- the third semiconductor layer has a jutting out region that juts out beyond an edge of the gate electrode toward a side where the drain electrode is provided.
A method of manufacturing a semiconductor device, comprising:
- sequentially depositing a first semiconductor layer and a second semiconductor layer on a substrate;
- forming a third semiconductor layer on the second semiconductor layer at a predetermined region, the third semiconductor layer including a p-type impurity element;
- forming a source electrode and a drain electrode in contact with the second semiconductor layer;
- and
- forming a gate electrode on the third semiconductor layer;
- wherein an edge of the third semiconductor layer on a drain electrode side is formed closer to the drain electrode than an edge of the gate electrode on the drain electrode side.
Dependencies are inferred from the claim text.