Manufacturing method for thin film transistor and thin film transistor manufactured by them
AssigneeSnu R&Db Foundation
InventorsMin Koo Han, Sun Jae Kim
Life of this patent
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Abstract
Provided are a manufacturing method for a thin film transistor, and a thin film transistor manufactured by the manufacturing method. In the manufacturing method, a semiconductor layer and an insulating layer for stopping etching, which are sequentially stacked, are etched by dry etching and wet etching using a single photoresist pattern, and patterning the semiconductor layer and the insulating layer into a channel layer and an etch stop layer, respectively, thereby simplifying the manufacturing process of the thin film transistor.
Claims20
A manufacturing method for a thin film transistor, comprising:
- preparing a substrate having a gate such that a gate insulating layer covering the gate and the substrate, a semiconductor layer and an insulating layer for stopping etching are sequentially formed on the substrate;
- forming a photoresist pattern such that the photoresist pattern is formed on the insulating layer for stopping etching, the photoresist pattern having a pattern corresponding to the gate;
- firstly etching such that the insulating layer for stopping etching and the semiconductor layer are etched using the photoresist pattern as a mask and patterned into an etch stop layer and a channel layer, respectively;
- secondly etching such that side surfaces of the etch stop layer disposed between the photoresist pattern and the channel layer are etched to expose opposite sides of the channel layer to the outside;
- removing a photoresist such that the photoresist pattern on the etch stop layer is removed;
- and
- forming a source/drain such that a source and a drain are formed at the opposite sides of the channel layer exposed to the outside in the secondly etching.
A thin film transistor comprising:
- a substrate;
- a gate formed on a top surface of the substrate;
- a gate insulating layer covering the gate and the top surface of the substrate;
- a channel layer formed on the gate insulating layer, the channel layer having a pattern corresponding to the gate;
- an etch stop layer formed on the channel layer, the width of the channel layer is greater than the width of the etch stop layer;
- a source/drain formed at the opposite sides of the channel layer;
- a passivation layer formed on the source/drain, etch stop layer and gate insulating layer, the passivation layer having a plurality of contact holes exposing electrodes of the source/drain;
- and
- a plurality of contacts formed in the contact holes and electrically connected to the source/drain.
Dependencies are inferred from the claim text.