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US 2013/0075589 A1Published application
Ramp wave generation circuit and solid-state imaging device
AssigneeOlympus Corporation
InventorYoshio Hagihara
Life of this patent
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Abstract
Provided are a ramp wave generation circuit and a solid-state imaging device in which a pulse output unit includes a delay part including a plurality of delay units that delay and output an input signal, and a delay control part that controls a delay time by which the delay unit delays the signal, and outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units, a time difference between timings at which the logic states of the respective signals are changed being a time corresponding to the delay time.
Claims5
A ramp wave generation circuit comprising:
- a pulse output unit including a delay part having a plurality of delay units that delay and output an input signal, and a delay control part controlling a delay time by which the delay unit delays a signal, wherein the pulse output unit outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units and a time corresponding to the delay time that a time difference between timings at which the logic states of the respective signals are changed is;
- m (m is a natural number greater than or equal to 2) functional circuits including an upper current source cell part having upper current source cells that generate a same constant current, a lower current source cell part having a plurality of lower current source cells weighted to generate a current value different by a predetermined percentage from a current value of the constant current generated by the upper current source cell, a lower bit selection part selecting the lower current source cell based on an output of the pulse output unit, and an upper bit selection part selecting the upper current source cell based on an output of the pulse output unit;
- an addition unit adding currents output from the m functional circuits;
- and
- a conversion unit converting an current added by the addition unit into a voltage and outputting the voltage,
- wherein a time difference between a timing of a selection operation of the lower bit selection part and the upper bit selection part had one functional circuit in the m functional circuits and a timing of a selection operation of the lower bit selection part and the upper bit selection part had the other functional circuit in the m functional circuits is a time corresponding to an integer times the delay time.
3 more elements
A ramp wave generation circuit comprising:
- a pulse output unit including a delay part having a plurality of delay units that delay and output an input signal, and a delay control part controlling a delay time by which the delay unit delays a signal, wherein the pulse output unit outputs a plurality of signals having logic states corresponding to logic states of signals output by the delay units and a time corresponding to the delay time that a time difference between timings at which the logic states of the respective signals are changed is;
- m (m is a natural number greater than or equal to 2) functional circuits including an upper current source cell part having upper current source cells that generate a same constant current, a lower current source cell part having a plurality of lower current source cells that generate a current value that is a predetermined percentage of a current value of the constant current generated by the upper current source cell, a lower bit selection part selecting the lower current source cell based on an output of the pulse output unit, and an upper bit selection part selecting the upper current source cell based on an output of the pulse output unit;
- an addition unit adding currents output from the m functional circuits;
- and
- a conversion unit converting an current added by the addition unit into a voltage and output the voltage,
- wherein a time difference between a timing of a selection operation of the lower bit selection part and the upper bit selection part had one functional circuit in the m functional circuits and a timing of a selection operation of the lower bit selection part and the upper bit selection part had the other functional circuit in the m functional circuits is a time corresponding to an integer times the delay time.
3 more elements
Dependencies are inferred from the claim text.