NMOS Buffer for High-Speed Low-Resolution Current Steering Digital-to-Analog Converters

A digital-to-analog converter (DAC), comprising:

• a thermometric decoder circuit that receives an n-bit binary code to accordingly output a plurality of digital signals representative of the n-bit binary code;
• and
• a plurality of unit cell circuits, at least one of the plurality of unit cell circuits comprising:
• a latch circuit coupled to receive clock signal and a respective one of the plurality of digital signals as a first digital signal, the latch circuit having an n-type metal-oxie-semiconductor (NMOS) field effect transistor-based buffer that outputs a buffered first digital signal and a buffered inverse first digital signal as an inverse of the buffered first digital signal, according to the clock signal;
• and
• a pair of differential p-type metal-oxide-semiconductor (PMOS) field effect transistors having a first PMOS transistor switched on or off according to the buffered first digital signal and a second PMOS transistor switched on or off according to the buffered inverse first digital signal such that the pair of differential PMOS transistors output an analog signal representative of the respective one of the plurality of digital signals from the thermometric decoder circuit.

A digital-to-analog converter (DAC), comprising:

• a unit cell that includes a pair of differential p-type metal-oxide-semiconductor (PMOS) field effect transistors coupled between a current source and a load, the pair of differential PMOS transistors including a first PMOS transistor and a second PMOS transistor such that when the first and second PMOS transistors are driven by a pair of complementary signals the pair of differential PMOS transistors outputs a corresponding analog signal;
• a latch circuit that receives and latches a digital signal and outputs, according to a clock signal, a pair of complementary digital signals corresponding to the latched digital signal;
• and
• a buffering circuit, coupled between the latch circuit and the pair of differential PMOS transistors, that buffers the pair of complementary digital signals and outputs a pair of equivalently fast rising and fast falling complementary signals that simultaneously drive the first and second PMOS transistors and output the analog signal.