Frequency Divider and Phase Locked Loop Including the Same

A phase locked loop (PLL), comprising:

• a phase frequency detector configured to generate an up signal and a down signal corresponding to a phase difference and a frequency difference between a reference signal and a feedback signal;
• a charge pump configured to generate a control current based on the up signal and the down signal;
• a loop filter configured to generate a control voltage by filtering the control current;
• a voltage controlled oscillator configured to generate an oscillation signal based on the control voltage;
• a first frequency divider configured to generate the feedback signal by dividing the oscillation signal;
• and
• a second frequency divider configured to generate an output signal by dividing the oscillation signal, the second frequency divider including:
• a first edge detection unit configured to generate a first count signal by detecting first edges of the oscillation signal based on a division control signal;
• a second edge detection unit configured to generate a second count signal by detecting the first edges of the oscillation signal or second edges of the oscillation signal based on a selection signal and the division control signal;
• a pulse triggered buffer unit configured to generate the output signal by controlling a logic level of an output node based on the first count signal and the second count signal, the output signal being divided by a target division ratio with respect to the oscillation signal;
• and
• a mode selection unit configured to set the target division ratio to an odd number division ratio or an even number division ratio based on the selection signal.