Methods and structures for controlling wafer curvature
AssigneeInternational Business Machines Corporation
InventorsMohammed Fazil Fayaz, Jeffery Burton Maxson, Anthony Kendall Stamper, Daniel Scott Vanslette
Life of this patent
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Abstract
Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
Claims20
A method, comprising:
- (a) selecting a wiring level design of an integrated circuit design, said design defining a physical wiring level of an integrated circuit chip on a wafer, wherein wires of said wiring level are formed of an electrical conductor in internal tensile stress and an interlevel dielectric layer of said wiring level is in internal tensile stress;
- after (a), (b) determining if an electrical conductor shape density of said wiring level design is within a pre-defined range;
- after (b), (c) if said electrical conductor shape density is below a lower limit of said range, increasing said electrical conductor shape density or if said electrical conductor shape density is greater than an upper limit of said range, decreasing said electrical conductor shape density;
- and
- after (c), (d) fabricating said one or more of said integrated circuit chips on said wafer using wiring level design.
A method, comprising:
- forming multiple wiring levels on a wafer from a first wiring level nearest said wafer to a last wiring level, each wiring level of said of multiple wiring levels comprising damascene wires in an interlevel dielectric layer;
- forming a terminal dielectric layer on said last wiring level of said multiple wiring levels;
- forming terminal pads on said terminal dielectric layer;
- forming a dielectric passivation layer on said terminal dielectric layer;
- forming a polyimide layer on said passivation layer, said polyimide layer internally in tensile stress;
- and
- forming vias and trenches in said polyimide layer, said terminal pads exposed in bottoms of said vias, said passivation layer but not said terminal pads exposed in bottoms of said trenches.
The method of claim 21, wherein said fill shapes result in dummy fill shapes the form in electrically conductive islands and said dummy wiring shapes result in electrically conductive dummy wires in said physical wiring level of said integrated circuit chip, said dummy fill shapes not electrically connected to any wire, dummy wire or other dummy fill shape of said physical wiring level, and said dummy wires not electrically connected to any wire, other dummy wire or dummy fill shape of said physical wiring level.
Dependencies are inferred from the claim text.