# US 2012/0278906 A1 · Systems and methods for detecting and mitigating programmable logic device tampering > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2012/0278906 A1 - Document ID: US20120278906A1 - Status: Published application - Kind: A1 - Application number: 13/098,074 - Filed: 2011-04-29 - Published: 2012-11-01 - Earliest claimed: 2011-04-29 - Assignees: Altera Corporation - Inventors: Bruce B. Pedersen - Web page: https://patentgrep.com/patent/US20120278906A1 ## CPC - G06F 21/86: Secure or tamper-resistant housings - G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] - H03K 19/17768: for security - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation. ## Claims ### Claim 1 A programmable integrated circuit device comprising: a register that is configured to store a dirty bit; and a control block that is configured to: determine a value of the dirty bit before beginning a configuration attempt, set the dirty bit to a set value if the value of the dirty bit is determined to be equal to a cleared value before beginning the configuration attempt, and initiate a first anti-tampering operation if the value of the dirty bit is determined to be equal to the set value before beginning the configuration attempt. ### Claim 2 (depends on 1) The programmable integrated circuit device of claim 1, wherein the control block is further configured to issue an alarm if the value of the dirty bit is determined to be equal to the set value before beginning the configuration attempt. ### Claim 3 (depends on 1) The programmable integrated circuit device of claim 1, wherein the control block is further configured to: modify an error counter value if the value of the dirty bit is determined to be equal to the set value before beginning the configuration attempt, and wherein the first anti-tampering operation occurs if the error counter value equals a first threshold value and if the value of the dirty bit is determined to be equal to the set value. ### Claim 4 (depends on 3) The programmable integrated circuit device of claim 3, wherein the control block is further configured to initiate a second anti-tampering operation when the error counter value equals a second threshold value, wherein the first threshold value is different from the second threshold value. ### Claim 5 (depends on 1) The programmable integrated circuit device of claim 1 further comprising logic circuitry that is configured to clear the dirty bit to a cleared value after successfully configuring the programmable integrated circuit device. ### Claim 6 (depends on 1) The programmable integrated circuit device of claim 1, wherein the first anti-tampering operation includes at least one of clearing a key stored in the programmable integrated circuit device and killing the programmable integrated circuit device. ### Claim 7 A method of mitigating tampering of a programmable integrated circuit device comprising: determining a value of the dirty bit before beginning a configuration attempt; setting the dirty bit to a set value if the value of the dirty bit is determined to be equal to a cleared value before beginning the configuration attempt; and initiating a first anti-tampering operation if the value of the dirty bit is determined to be equal to the set value before beginning the configuration attempt. ### Claim 8 (depends on 7) The method of claim 7 further comprising issuing an alarm if the value of the dirty bit is determined to be equal to the set value before beginning the configuration attempt. ### Claim 9 (depends on 7) The method of claim 7 further comprising: modifying an error counter value if the value of the dirty bit is determined to be equal to the set value before beginning the configuration attempt, wherein the first anti-tampering operation occurs if the error counter value equals a first threshold value and if the value of the dirty bit is determined to be equal to the set value. ### Claim 10 (depends on 9) The method of claim 9 further comprising initiating a second anti-tampering operation when the error counter value equals a second threshold value, wherein the first threshold value is different from the second threshold value. ### Claim 11 (depends on 7) The method of claim 7, wherein the first anti-tampering operation includes at least one of clearing a key stored in the programmable integrated circuit device and killing the programmable integrated circuit device. ### Claim 12 (depends on 7) The method of claim 7 further comprising clearing the dirty bit to a cleared value after successfully configuring the programmable integrated circuit device using logic circuitry. ### Claim 13 A programmable integrated circuit device comprising: a register that is configured to store a value of an error counter; and a control block that is configured to: configure the programmable integrated circuit device, modify the value of the error counter in response to an unsuccessful configuration attempt, determine whether the value of the error counter equals a first threshold, and initiate a first anti-tampering operation in response to the value of the error counter equaling the first threshold. ### Claim 14 (depends on 13) The programmable integrated circuit device of claim 13 further comprising logic circuitry configured to reset the value of the error counter after a configuration attempt completes successfully. ### Claim 15 (depends on 13) The programmable integrated circuit device of claim 13, wherein the control block is further configured to determine whether the value of the error counter equals a second threshold. ### Claim 16 (depends on 15) The programmable integrated circuit device of claim 15, wherein the control block is further configured to initiate a second anti-tampering operation when the value of the error counter is determined to equal the second threshold, wherein the first anti-tampering operation and the second anti-tampering operation are different. ### Claim 17 (depends on 13) The programmable integrated circuit device of claim 13, wherein modifying the value of the error counter includes at least one of incrementing and decrementing the value of the error counter. ### Claim 18 A method of mitigating tampering of a programmable integrated circuit device comprising: receiving an initiation signal to configure the programmable integrated circuit device; modifying a value of an error counter in response to an unsuccessful attempt to configure the programmable integrated circuit device if the value of the error counter has been previously set; determining whether the value of the error counter equals a first threshold; and initiating a first anti-tampering operation in response to the value of the error counter equaling the first threshold. ### Claim 19 (depends on 18) The method of claim 18 further comprising resetting the value of the error counter after a configuration attempt completes successfully. ### Claim 20 (depends on 18) The method of claim 18 further comprising determining whether the value of the error counter equals a second threshold. ### Claim 21 (depends on 20) The method of claim 20 further comprising initiating a second anti-tampering operation when the value of the error counter is determined to equal the second threshold, wherein the first anti-tampering operation and the second anti-tampering operation are different. ### Claim 22 (depends on 18) The method of claim 18, wherein modifying the value of the error counter includes at least one of incrementing and decrementing the value of the error counter.