Timing error sampling generator and a method of timing testing

A method of performing a timing test on a path, comprising:

• generating a comparison signal based on a data signal from said path and a clocked data signal;
• generating a clock hold signal employing first logic circuitry and a hold delay element that provides a first predetermined delay corresponding to a hold violation time for said path;
• and
• providing an error hold signal based on said comparison signal and said clock hold signal to indicate a hold violation of said path.

A library of standard logic elements, comprising:

• a standard logic element corresponding to a timing error sampling generator, including:
• a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored;
• and
• a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.