Method and Apparatus for Generating Memory Models and Timing Database

A method comprising:

• (a) accessing, with a computer, a timing database for a set of characterization memories, each characterization memory having different memory parameters, the timing database comprising timing characteristics for each of a plurality of variants of tiling each of the characterization memories to a memory resource on an integrated circuit, each variant of tiling each characterization memory to the memory resource being referred to as a tiling netlist, wherein the timing characteristics comprise, for each tiling netlist:
• evaluated timing characteristics corresponding to a first subset of combinations of input ramptimes and output loads of the tiling netlist;
• and
• estimated timing characteristics corresponding to a second, different subset of combinations of input ramptimes and output loads of the tiling netlist, which are mathematical functions of at least one of the timing characteristics for the first subset;
• and
• (b) with the computer, assigning to a design memory having a known tiling variant the timing characteristics of the known tiling variant of a corresponding characterization memory in the timing database.

An apparatus comprising:

• a processor configured to:
• access a computer-readable medium comprising a timing database stored thereon for a set of characterization memories, each characterization memory having different memory parameters, the timing database comprising timing characteristics for each of a plurality of variants of tiling each of the characterization memories to a memory resource on an integrated circuit, each variant of tiling each characterization memory to the memory resource being referred to as a tiling netlist, wherein the timing characteristics comprise, for each tiling netlist:
• evaluated timing characteristics corresponding to a first subset of combinations of input ramptimes and output loads of the tiling netlist;
• and
• estimated timing characteristics corresponding to a second, different subset of combinations of input ramptimes and output loads of the tiling netlist, which are mathematical functions of at least one of the timing characteristics for the first subset;
• compare memory parameters of a design memory having a known tiling variant with those of the characterization memories to identify a corresponding characterization memory;
• and
• assign the timing characteristics of the known tiling variant of the corresponding characterization memory to the design memory.

A non-transmission type computer-readable medium comprising instructions stored thereon, which when executed by a processor configure the processor to perform a method comprising:

• accessing a timing database comprising a set of characterization memories, each characterization memory having different memory parameters, the timing database comprising timing characteristics for each of a plurality of variants of tiling each of the characterization memories to a memory resource on an integrated circuit, each variant of tiling each characterization memory to the memory resource being referred to as a tiling netlist, wherein the timing characteristics comprise, for each tiling netlist:
• evaluated timing characteristics corresponding to a first subset of combinations of input ramptimes and output loads of the tiling netlist;
• and
• estimated timing characteristics corresponding to a second, different subset of combinations of input ramptimes and output loads of the tiling netlist, which are mathematical functions of at least one of the timing characteristics for the first subset;
• comparing memory parameters of a design memory having a known tiling variant with those of the characterization memories to identify a corresponding characterization memory;
• and
• assigning the timing characteristics of the known tiling variant of the corresponding characterization memory to the design memory.