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US 2012/0269255 A1Published application
Parallel Closed-Loop DFE Filter Architecture
AssigneeSTMicroelectronics (Canada) Inc.
InventorsAnton Pelteshki, John Hogeboom
Life of this patent
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Abstract
A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.
Claims20
A DFE filter comprising:
- an input;
- a first filter loop coupled to the input for providing an odd bit-stream;
- and
- a second filter loop coupled to the input for providing an even bit-stream.
1 more element
A DFE filter comprising:
- an input;
- a first filter loop including a multi-tap delay circuit coupled to the input for providing an odd bit-stream;
- and
- a second filter loop coupled to the input for providing an even bit-stream.
1 more element
A DFE filter comprising:
- an input;
- a first filter loop coupled to the input for providing an odd bit-stream;
- and
- a second filter loop including a multi-tap delay circuit coupled to the input for providing an even bit-stream.
1 more element
Dependencies are inferred from the claim text.