High speed and high jitter tolerance dispatcher
AssigneesSTMicroelectronics S.r.l., Université De Monastir
InventorsMounir Zid, Alberto Scandurra, Carmelo Pistritto, Rached Tourki
Life of this patent
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Abstract
A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.
Claims24
A circuit, comprising:
- demultiplexer circuitry configured to receive data from an input and output a plurality of divided data outputs, and
- multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry.
A circuit, comprising:
- a first demultiplexer having an input configured to receive a serialized data stream and a first and second output configured to produce a first and second divided data stream;
- a second demultiplexer having an input configured to receive the first divided data stream and a first and second output configured to produce a third and fourth divided data stream;
- a third demultiplexer having an input configured to receive the second divided data stream and a first and second output configured to produce a fifth and sixth divided data stream;
- a first multiplexer having a control terminal configured to receive the third divided data stream and a output configured to produce a first parallel data bit;
- a second multiplexer having a control terminal configured to receive the fourth divided data stream and a output configured to produce a second parallel data bit;
- a third multiplexer having a control terminal configured to receive the fifth divided data stream and a output configured to produce a third parallel data bit;
- and
- a fourth multiplexer having a control terminal configured to receive the sixth divided data stream and a output configured to produce a fourth parallel data bit.
A circuit, comprising:
- demultiplexer circuitry having an input configured to receive a serialized data stream including a plurality of channels and further having a plurality of outputs equal in number to said plurality of channels, each output configured to produce a divided data signal, and
- a plurality of multiplexers equal in number to said plurality of channels, each multiplexer having a first input configured to receive a first logic level signal, a second input configured to receive a second logic level signal, and a control input configured to receive one of said divided data signals, a plurality of outputs from said plurality of multiplexers configured to output data from said received serialized data stream in a parallel form.
Dependencies are inferred from the claim text.