Delay circuit and latency control circuit of memory, and signal delay method thereof
AssigneeHynix Semiconductor Inc.
InventorJeong-Tae HWANG
Life of this patent
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Abstract
A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.
Claims24
A delay circuit, comprising:
- a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal;
- a distinguishment signal generation unit configured to generate a distinguishment signal that represents to which signal the transfer signal corresponds to between the first signal or the second signal;
- and
- a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.
A latency control circuit of a memory device, comprising:
- a command signal delay unit configured to generate a delayed command signal by delaying a command signal corresponding to a read command or a write command by a latency;
- a distinguishment signal generation unit configured to generate a distinguishment signal that represents to which singal the command signal corresponds to between the read command or the write command;
- and
- a delayed command generation unit configured to output the delayed command signal as a delayed read command or a delayed write command in response to the distinguishment signal.
A latency control circuit of a memory device, comprising:
- a command delay unit configured to generate a delayed command by delaying an inputted command between a read command and a write command by a latency;
- and
- a command distinguishment unit configured to distinguish which command is inputted to the command delay unit between the read command and a write command.
A method for delaying a signal, comprising:
- generating a transfer signal corresponding to a signal when a first signal or a second signal is applied;
- generating a distinguishment signal that represents to what signal the transfer signal correspond between the first signal and the second signal;
- generating a delayed transfer signal by delaying the transfer signal;
- and
- outputting the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.
Dependencies are inferred from the claim text.