Latency control circuit, latency control method thereof, and semiconductor memory device including the same
AssigneeHynix Semiconductor Inc.
InventorsMin-Su PARK, Jae-Il Kim
Life of this patent
Estimating the term…
Abstract
A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.
Claims33
A latency control circuit of a semiconductor device, comprising:
- a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock;
- a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information;
- and
- a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock.
A semiconductor memory device, comprising:
- a delay locked loop unit configured to generate an internal clock by delaying an external clock;
- a phase detection unit configured to generate phase information regarding a phase difference between the external clock and the internal clock;
- a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information;
- a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock;
- and
- a data input/output unit configured to perform a data input/output operation in response to the latency signal.
A method for controlling a latency, comprising:
- generating path information of a semiconductor device in response to a delay amount reset signal;
- generating phase information regarding a phase difference between an external clock and an internal clock;
- deciding a latency delay amount based on a latency value of an input signal, the path information, and the phase information;
- delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal;
- and
- generating a latency signal by synchronizing the delayed input signal with the internal clock.
Dependencies are inferred from the claim text.