Memory device and method for operating the same

A memory comprising:

• first flag cells configured to store first flag data;
• second flag cells configured to store second flag data;
• third flag cells configured to store third flag data;
• first sensing nodes having voltage levels determined by the first flag data of the first flag cells, respectively;
• second sensing nodes having voltage levels determined by the second flag data of the second flag cells, respectively;
• third sensing nodes having voltage levels determined by the third flag data of the third flag cells, respectively;
• a selection circuit configured to select the first sensing nodes or the second sensing nodes in response to a flag address;
• and
• a determination circuit having a first internal node through which current corresponding to voltage levels of selected sensing nodes flows and a second internal node through which current corresponding to the voltage levels of the third sensing nodes flows, wherein the determination circuit is configured to determine a logic value of flag data corresponding to the selected sensing nodes among the first and second flag data by using the amount of current flowing through the first internal node and determine a logic value of the third flag data by using the amount of current flowing through the second internal node.

A method for operating a memory including at least one first flag cell for storing first flag data and at least one second flag cell for storing second flag data, comprising:

• selecting the first flag cell or the second flag cell in response to a flag address;
• generating current corresponding to a value stored in a selected flag cell;
• and
• comparing an amount of generated current with a reference current amount and determining a logic value of flag data stored in the selected flag cell.

A memory comprising:

• a plurality of memory cells configured to store multi-bit data;
• a plurality of flag cell regions, each flag cell region comprising a plurality of flag cells, configured to store flag data, the flag data indicating that a certain bit of the multi-bit data is programmed to the plurality of memory cells;
• a plurality of sensing node groups each comprising sensing nodes corresponding to the flag cells and having a voltage level determined by the corresponding flag data;
• and
• a determination circuit having current paths corresponding to the sensing node groups,
• wherein each current path is formed in response to a voltage level of the corresponding sensing node group, when the corresponding sensing node group is selected,
• wherein the determination circuit is configured to determine a logic value of flag data corresponding to the selected sensing node group by using an amount of current flowing through the corresponding current path.