Programming method for nonvolatile memory device

A method of programming a plurality of memory transistors on a word line of a nonvolatile memory device, comprising:

• programming the third and fourth memory transistors to one logic state of a first set of logic states, including:
• a first program step of applying a first program voltage to the third and fourth memory transistors;
• and
• a first verify step of applying a first target verification voltage to the third and fourth memory transistors for verifying that the third and fourth memory transistors are programmed to the second logic state of the first set of logic states;
• and then
• programming the second, third and fourth memory transistors to three logic states of a second set of logic states, including:
• a second program step of applying a second program voltage to the second memory transistor for programming the second memory transistor to the second logic state of the second set of logic states;
• a third program step of applying a third program voltage to the third memory transistor for programming the third memory transistor to the third logic state of the second set of logic states;
• a second verify step of applying a second target verification voltage to the second memory transistor for verifying that the second memory transistor is programmed to the second logic state of the second set of logic states, and
• wherein the second verify step comprises applying the second target verification voltage to the third memory transistor for using the second target verification voltage as a pre-verification voltage for the third memory transistor.