Non-volatile semiconductor memory device and electronic apparatus

A non-volatile semiconductor memory device for detecting a degree of a degradation over time due to an operating temperature and an operating time, comprising:

• a memory cell array including a plurality of non-volatile memory cells;
• a plurality of word lines connected to gates of the plurality of non-volatile memory cells;
• a plurality of bit lines connected to drains or sources of the plurality of non-volatile memory cells;
• a word line select circuit configured to select one of the plurality of word lines and apply a voltage to the selected word line;
• a bit line select circuit configured to select one of the plurality of bit lines and apply a voltage to the selected bit line;
• a sense amplifier circuit configured to detect a state of a non-volatile memory cell selected by the word line select circuit and the bit line select circuit;
• and
• a control circuit configured to control the non-volatile semiconductor memory device,
• wherein
• the memory cell array is divided into a first block including a non-volatile memory cell for accumulating the degradation over time and a second block including a non-volatile memory cell for storing data, and
• the word line select circuit and the bit line select circuit select a word line or a bit line connected to the first block to apply a stress voltage to the non-volatile memory cell for accumulating the degradation over time of the first block during a period of time that a power supply voltage is being applied to the non-volatile semiconductor memory device.

A non-volatile semiconductor memory device for detecting a degree of a degradation over time due to an operating temperature and an operating time, comprising:

• a memory cell array including a plurality of non-volatile memory cells;
• a plurality of word lines connected to gates of the plurality of non-volatile memory cells;
• a plurality of bit lines connected to drains or sources of the plurality of non-volatile memory cells;
• a word line select circuit configured to select one of the plurality of word lines and apply a voltage to the selected word line;
• a bit line select circuit configured to select one of the plurality of bit lines and apply a voltage to the selected bit line;
• a sense amplifier circuit configured to detect a state of a non-volatile memory cell selected by the word line select circuit and the bit line select circuit;
• and
• a control circuit configured to control the non-volatile semiconductor memory device,
• wherein
• the memory cell array is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data, and
• the word line select circuit and the bit line select circuit select a first word line and a first bit line connected to the second block to access the non-volatile memory cell for storing data of the second block, and selects a second word line or a second bit line, of the plurality of word lines and the plurality of bit lines connected to the first block, to apply a stress voltage to a non-volatile memory cell for accumulating a first degradation over time of the first block, and do not select a third word line or a third bit line, of the plurality of word lines and the plurality of bit lines connected to the first block, and therefore do not apply a stress voltage to a non-volatile memory cell for accumulating a second degradation over time of the first block.

A non-volatile semiconductor memory device for detecting a degree of a degradation over time due to an operating temperature and an operating time, comprising:

• a memory cell array including a plurality of non-volatile memory cells;
• a plurality of word lines connected to gates of the plurality of non-volatile memory cells;
• a plurality of bit lines connected to drains or sources of the plurality of non-volatile memory cells;
• a word line select circuit configured to select one of the plurality of word lines and apply a voltage to the selected word line;
• a bit line select circuit configured to select one of the plurality of bit lines and apply a voltage to the selected bit line;
• a sense amplifier circuit configured to detect a state of a non-volatile memory cell selected by the word line select circuit and the bit line select circuit;
• and
• a control circuit configured to control the non-volatile semiconductor memory device,
• wherein
• the memory cell array is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data, and
• the word line select circuit and the bit line select circuit select a first word line or a first bit line, of the plurality of word lines and the plurality of bit lines connected to the first block, to apply a stress voltage to a non-volatile memory cell for accumulating a first degradation over time of the first block, and do not select a second word line or a second bit line, of the plurality of word lines and the plurality of bit lines connected to the first block, and therefore do not apply a stress voltage to a non-volatile memory cell for accumulating a second degradation over time of the first block, during a period of time that a power supply voltage is being applied to the non-volatile semiconductor memory device.

A semiconductor integrated circuit comprising:

• a non-volatile semiconductor memory device configured to detect a degree of a degradation over time due to an operating temperature and an operating time;
• and
• a central processing device configured to control an apparatus,
• wherein
• the non-volatile semiconductor memory device and the central processing device are provided on a same semiconductor substrate, and
• the non-volatile semiconductor memory device outputs to the central processing device a detection signal indicating that the degradation over time has proceeded.

A semiconductor integrated circuit comprising:

• a non-volatile semiconductor memory device configured to detect a degree of a degradation over time due to an operating temperature and an operating time;
• and
• a central processing device configured to control an apparatus,
• wherein
• the non-volatile semiconductor memory device outputs to the central processing device a detection signal indicating that the degradation over time has proceeded.