Memory system
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki NAGASHIMA
Life of this patent
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Abstract
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
Claims19
A memory system comprising:
- a nonvolatile semiconductor memory device including
- a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell;
- and
- a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,
- wherein the control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
A memory system comprising:
- a nonvolatile semiconductor memory device including
- a memory cell array having a plurality of blocks each including a plurality of memory cells, and
- a voltage generation unit configured to change a read level of the memory cell;
- and
- a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,
- wherein the control unit includes an error detection unit configured to detect an error from read data, and
- performs retry read to repeat read again when the error detection unit has detected an error.
A memory system comprising:
- a nonvolatile semiconductor memory device including
- a memory cell array having a plurality of blocks each including a plurality of memory cells, and
- a voltage generation unit configured to change a read level of the memory cell;
- and
- a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,
- wherein the control unit includes an error detection unit configured to detect an error from read data, and
- a management area configured to record management data, and
- when the error detection unit has detected an error, the control unit performs retry read using a read level shifted to be higher than an original read level of the memory cell and a read level lower than the original read level, and records, in the management area, data of a read level corresponding to a satisfactory result of the retry read.
A memory system comprising:
- a nonvolatile semiconductor memory device including
- a memory cell array having a plurality of blocks each including a plurality of memory cells, and
- a voltage generation unit configured to change a read level of the memory cell;
- and
- a control unit configured to control write, read, and erase of the nonvolatile semiconductor memory device,
- wherein the control unit includes an error detection unit configured to detect an error from read data, and
- when the error detection unit has detected an error, the control unit performs a read operation using a read level shifted to be higher than an original read level of the memory cell, and if the number of errors proves to be small as a result of determination of the error detection unit, performs the next read operation using the read level shifted to be higher.
Dependencies are inferred from the claim text.