Semiconductor memory device

Abstract

A semiconductor memory device includes first and second memory planes that each include a plurality of memory blocks, a first page buffer group coupled to the memory blocks of the first memory plane through first bit lines and configured to perform a read operation and a program operation, a second page buffer group coupled to the memory blocks of the second memory plane through second bit lines and configured to perform the read operation and the program operation, a coupling circuit configured to couple the first bit lines of the first memory planes and the second bit lines of the second memory planes, respectively, in response to a coupling signal, and a control circuit configured to generate the coupling signal for controlling the coupling circuit in a copyback operation of data, read from a source page of the first memory plane, in a target page of the second memory plane.

Dependencies are inferred from the claim text.