Semiconductor memory device in which capacitance between bit lines is reduced, and method of manufacturing the same

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix;
• a plurality of word lines configured to select the plurality of memory cells;
• and
• a plurality of bit lines configured to select the plurality of memory cells,
• wherein among a first bit line, a second bit line, a third bit line, and a fourth bit line adjacent to each other in the plurality of bit lines, the first bit line and the third bit line are formed in a first interconnection layer, and the second bit line and the fourth bit line are formed in a second interconnection layer.

A semiconductor memory device manufacturing method comprising:

• forming, on a first insulating film, a first film having a width larger than a width of a bit line to be formed;
• forming a second film by slimming the first film into the width of the bit line to be formed;
• forming second insulating films on sidewalls of the second film;
• forming a first trench having a first depth in the first insulating film by using the second film and the second insulating films as masks;
• forming a first bit line in the first trench by using a first conductive material;
• filling the first trench with a third insulating film;
• removing the second film;
• forming a second trench shallower than the first depth in the first insulating film by using the second insulating films as masks;
• and
• forming a second bit line in the second trench by using a second conductive material.